diff options
Diffstat (limited to 'drivers/staging/r8188eu/include')
34 files changed, 49 insertions, 1508 deletions
diff --git a/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h b/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h index 6f901ce607e8..2517a08bc95a 100644 --- a/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h +++ b/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h @@ -4,37 +4,11 @@ #ifndef __INC_HAL8188EPHYCFG_H__ #define __INC_HAL8188EPHYCFG_H__ -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM 9 -#define HP_THERMAL_NUM 8 - #define MAX_AGGR_NUM 0x07 -/*--------------------------Define Parameters-------------------------------*/ - -/*------------------------------Define structure----------------------------*/ - -enum hw90_block { - HW90_BLOCK_MAC = 0, - HW90_BLOCK_PHY0 = 1, - HW90_BLOCK_PHY1 = 2, - HW90_BLOCK_RF = 3, - HW90_BLOCK_MAXIMUM = 4, /* Never use this */ -}; - enum rf_radio_path { RF_PATH_A = 0, /* Radio Path A */ RF_PATH_B = 1, /* Radio Path B */ - RF_PATH_C = 2, /* Radio Path C */ - RF_PATH_D = 3, /* Radio Path D */ }; #define MAX_PG_GROUP 13 @@ -46,17 +20,6 @@ enum rf_radio_path { #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, *ch9~11, ch12~13, CH 14 * total three groups */ -#define CHANNEL_GROUP_MAX_88E 6 - -/* BB/RF related */ -enum RF_TYPE_8190P { - RF_TYPE_MIN, /* 0 */ - RF_8225 = 1, /* 1 11b/g RF for verification only */ - RF_8256 = 2, /* 2 11b/g/n */ - RF_6052 = 4, /* 4 11b/g/n RF */ - /* TODO: We should remove this psudo PHY RF after we get new RF. */ - RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ -}; struct bb_reg_def { u32 rfintfs; /* set software control: */ @@ -106,18 +69,7 @@ struct bb_reg_def { * Path A and B */ }; -/*------------------------------Define structure----------------------------*/ - -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ - -/*------------------------Export Marco Definition---------------------------*/ -/*------------------------Export Marco Definition---------------------------*/ - -/*--------------------------Exported Function prototype---------------------*/ -/* */ /* BB and RF register read/write */ -/* */ u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask); void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 mask, u32 data); @@ -144,15 +96,5 @@ void PHY_SwChnl8188E(struct adapter *adapter, u8 channel); void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr, u32 mask, u32 data); -/*--------------------------Exported Function prototype---------------------*/ - -#define PHY_QueryBBReg(adapt, regaddr, mask) \ - rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask)) -#define PHY_SetBBReg(adapt, regaddr, bitmask, data) \ - rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data)) -#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \ - rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask)) -#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \ - rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data)) -#endif /* __INC_HAL8192CPHYCFG_H */ +#endif diff --git a/drivers/staging/r8188eu/include/Hal8188EPwrSeq.h b/drivers/staging/r8188eu/include/Hal8188EPwrSeq.h index a73bd1a5d57b..e4c5b5d23cb4 100644 --- a/drivers/staging/r8188eu/include/Hal8188EPwrSeq.h +++ b/drivers/staging/r8188eu/include/Hal8188EPwrSeq.h @@ -6,150 +6,8 @@ #include "HalPwrSeqCmd.h" -/* - Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END - - PWR SEQ Version: rtl8188E_PwrSeq_V09.h -*/ -#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 -#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 -#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8188E_TRANS_END_STEPS 1 - -#define RTL8188E_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, /* 0x02[1:0] = 0 reset BB*/ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x04[8] = 1 polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, /*wait till 0x04[8] = 0*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/ \ - {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/ \ - -#define RTL8188E_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - -#define RTL8188E_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ - -#define RTL8188E_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ - -/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ -#define RTL8188E_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ - -#define RTL8188E_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8188E_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0, PWR_CMD_END, 0, 0}, /* */ - -extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_power_on_flow[]; +extern struct wl_pwr_cfg rtl8188E_card_disable_flow[]; +extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[]; #endif /* __HAL8188EPWRSEQ_H__ */ diff --git a/drivers/staging/r8188eu/include/HalPhyRf_8188e.h b/drivers/staging/r8188eu/include/HalPhyRf_8188e.h index d4a27662309f..b75a5d869c56 100644 --- a/drivers/staging/r8188eu/include/HalPhyRf_8188e.h +++ b/drivers/staging/r8188eu/include/HalPhyRf_8188e.h @@ -30,12 +30,7 @@ void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter); void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum); -void _PHY_PathADDAOn(struct adapter *pAdapter, u32 *ADDAReg, - bool isPathAOn, bool is2T); - void _PHY_MACSettingCalibration(struct adapter *pAdapter, u32 *MACReg, u32 *MACBackup); -void _PHY_PathAStandBy(struct adapter *pAdapter); - #endif /* #ifndef __HAL_PHY_RF_8188E_H__ */ diff --git a/drivers/staging/r8188eu/include/HalPwrSeqCmd.h b/drivers/staging/r8188eu/include/HalPwrSeqCmd.h index fe7ac910beb8..49c02cce569e 100644 --- a/drivers/staging/r8188eu/include/HalPwrSeqCmd.h +++ b/drivers/staging/r8188eu/include/HalPwrSeqCmd.h @@ -9,11 +9,6 @@ /*---------------------------------------------*/ /* 3 The value of cmd: 4 bits */ /*---------------------------------------------*/ -#define PWR_CMD_READ 0x00 - /* offset: the read register offset */ - /* msk: the mask of the read value */ - /* value: N/A, left by 0 */ - /* note: dirver shall implement this function by read & msk */ #define PWR_CMD_WRITE 0x01 /* offset: the read register offset */ @@ -41,43 +36,6 @@ /* msk: N/A */ /* value: N/A */ -/*---------------------------------------------*/ -/* 3 The value of base: 4 bits */ -/*---------------------------------------------*/ - /* define the base address of each block */ -#define PWR_BASEADDR_MAC 0x00 -#define PWR_BASEADDR_USB 0x01 -#define PWR_BASEADDR_PCIE 0x02 -#define PWR_BASEADDR_SDIO 0x03 - -/*---------------------------------------------*/ -/* 3 The value of interface_msk: 4 bits */ -/*---------------------------------------------*/ -#define PWR_INTF_SDIO_MSK BIT(0) -#define PWR_INTF_USB_MSK BIT(1) -#define PWR_INTF_PCI_MSK BIT(2) -#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -/* 3 The value of fab_msk: 4 bits */ -/*---------------------------------------------*/ -#define PWR_FAB_TSMC_MSK BIT(0) -#define PWR_FAB_UMC_MSK BIT(1) -#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -/* 3 The value of cut_msk: 8 bits */ -/*---------------------------------------------*/ -#define PWR_CUT_TESTCHIP_MSK BIT(0) -#define PWR_CUT_A_MSK BIT(1) -#define PWR_CUT_B_MSK BIT(2) -#define PWR_CUT_C_MSK BIT(3) -#define PWR_CUT_D_MSK BIT(4) -#define PWR_CUT_E_MSK BIT(5) -#define PWR_CUT_F_MSK BIT(6) -#define PWR_CUT_G_MSK BIT(7) -#define PWR_CUT_ALL_MSK 0xFF - enum pwrseq_cmd_delat_unit { PWRSEQ_DELAY_US, PWRSEQ_DELAY_MS, @@ -85,26 +43,17 @@ enum pwrseq_cmd_delat_unit { struct wl_pwr_cfg { u16 offset; - u8 cut_msk; - u8 fab_msk:4; - u8 interface_msk:4; - u8 base:4; u8 cmd:4; u8 msk; u8 value; }; #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset -#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk -#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk -#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk -#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value /* Prototype of protected function. */ -u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 CutVersion, u8 FabVersion, - u8 InterfaceType, struct wl_pwr_cfg PwrCfgCmd[]); +u8 HalPwrSeqCmdParsing(struct adapter *padapter, struct wl_pwr_cfg PwrCfgCmd[]); #endif diff --git a/drivers/staging/r8188eu/include/HalVerDef.h b/drivers/staging/r8188eu/include/HalVerDef.h index 796a44a1e697..62b94c993f0d 100644 --- a/drivers/staging/r8188eu/include/HalVerDef.h +++ b/drivers/staging/r8188eu/include/HalVerDef.h @@ -24,22 +24,10 @@ enum HAL_VENDOR { CHIP_VENDOR_UMC = 1, }; -enum HAL_RF_TYPE { - RF_TYPE_1T1R = 0, - RF_TYPE_1T2R = 1, - RF_TYPE_2T2R = 2, - RF_TYPE_2T3R = 3, - RF_TYPE_2T4R = 4, - RF_TYPE_3T3R = 5, - RF_TYPE_3T4R = 6, - RF_TYPE_4T4R = 7, -}; - struct HAL_VERSION { enum HAL_CHIP_TYPE ChipType; enum HAL_CUT_VERSION CUTVersion; enum HAL_VENDOR VendorType; - enum HAL_RF_TYPE RFType; u8 ROMVer; }; @@ -47,7 +35,6 @@ struct HAL_VERSION { #define GET_CVID_CHIP_TYPE(version) (((version).ChipType)) #define GET_CVID_MANUFACTUER(version) (((version).VendorType)) #define GET_CVID_CUT_VERSION(version) (((version).CUTVersion)) -#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK) /* Common Macro. -- */ /* HAL_VERSION VersionID */ diff --git a/drivers/staging/r8188eu/include/drv_types.h b/drivers/staging/r8188eu/include/drv_types.h index 3e4928320f17..2dd5ebaaa921 100644 --- a/drivers/staging/r8188eu/include/drv_types.h +++ b/drivers/staging/r8188eu/include/drv_types.h @@ -34,6 +34,7 @@ #include "rtw_p2p.h" #include "rtw_ap.h" #include "rtw_br_ext.h" +#include "rtl8188e_hal.h" #define DRIVERVERSION "v4.1.4_6773.20130222" @@ -85,7 +86,6 @@ struct registry_priv { u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */ u8 lowrate_two_xmit; - u8 rf_config; u8 low_power; u8 wifi_spec;/* !turbo_mode */ @@ -114,12 +114,6 @@ struct registry_priv { u8 notch_filter; }; -/* For registry parameters */ -#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field)) -#define RGTRY_SZ(field) sizeof(((struct registry_priv *)0)->field) -#define BSSID_OFT(field) ((u32)FIELD_OFFSET(struct wlan_bssid_ex, field)) -#define BSSID_SZ(field) sizeof(((struct wlan_bssid_ex *)0)->field) - #define MAX_CONTINUAL_URB_ERR 4 struct rt_firmware { @@ -129,14 +123,13 @@ struct rt_firmware { struct dvobj_priv { struct adapter *if1; - struct adapter *if2; /* For 92D, DMDP have 2 interface. */ u8 InterfaceNumber; u8 NumInterfaces; /* In /Out Pipe information */ - int RtInPipe[2]; + int RtInPipe; int RtOutPipe[3]; u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ @@ -146,11 +139,8 @@ struct dvobj_priv { /*-------- below is for USB INTERFACE --------*/ - u8 nr_endpoint; u8 ishighspeed; - u8 RtNumInPipes; u8 RtNumOutPipes; - int ep_num[5]; /* endpoint number */ int RegUsbSS; struct semaphore usb_suspend_sema; struct mutex usb_vendor_req_mutex; @@ -210,8 +200,7 @@ struct adapter { struct hostapd_priv *phostapdpriv; struct wifidirect_info wdinfo; - void *HalData; - u32 hal_data_sz; + struct hal_data_8188e haldata; s32 bDriverStopped; s32 bSurpriseRemoved; @@ -275,8 +264,6 @@ struct adapter { unsigned char br_ip[4]; struct br_ext_info ethBrExtInfo; - u8 fix_rate; - unsigned char in_cta_test; }; diff --git a/drivers/staging/r8188eu/include/hal_intf.h b/drivers/staging/r8188eu/include/hal_intf.h index d777ad9071e2..b4a7e0ce3116 100644 --- a/drivers/staging/r8188eu/include/hal_intf.h +++ b/drivers/staging/r8188eu/include/hal_intf.h @@ -29,7 +29,6 @@ enum hw_variables { HW_VAR_ACK_PREAMBLE, HW_VAR_SEC_CFG, HW_VAR_BCN_VALID, - HW_VAR_RF_TYPE, HW_VAR_DM_FLAG, HW_VAR_DM_FUNC_OP, HW_VAR_DM_FUNC_SET, @@ -95,40 +94,17 @@ enum hal_def_variable { HAL_DEF_DBG_DUMP_TXPKT, }; -enum hal_odm_variable { - HAL_ODM_STA_INFO, - HAL_ODM_P2P_STATE, - HAL_ODM_WIFI_DISPLAY_STATE, -}; - typedef s32 (*c2h_id_filter)(u8 id); -#define RF_CHANGE_BY_INIT 0 -#define RF_CHANGE_BY_IPS BIT(28) -#define RF_CHANGE_BY_PS BIT(29) -#define RF_CHANGE_BY_HW BIT(30) -#define RF_CHANGE_BY_SW BIT(31) - #define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) -void rtl8188eu_alloc_haldata(struct adapter *adapt); - void rtl8188eu_interface_configure(struct adapter *adapt); void ReadAdapterInfo8188EU(struct adapter *Adapter); void rtl8188eu_init_default_value(struct adapter *adapt); -void rtl8188e_SetHalODMVar(struct adapter *Adapter, - enum hal_odm_variable eVariable, void *pValue1, bool bSet); +void rtl8188e_SetHalODMVar(struct adapter *Adapter, void *pValue1, bool bSet); u32 rtl8188eu_InitPowerOn(struct adapter *adapt); -void rtl8188e_free_hal_data(struct adapter *padapter); -void rtl8188e_EfusePowerSwitch(struct adapter *pAdapter, u8 bWrite, u8 PwrState); -void rtl8188e_ReadEFuse(struct adapter *Adapter, u8 efuseType, - u16 _offset, u16 _size_byte, u8 *pbuf, - bool bPseudoTest); -void rtl8188e_EFUSE_GetEfuseDefinition(struct adapter *pAdapter, u8 efuseType, - u8 type, void *pOut, bool bPseudoTest); -u16 rtl8188e_EfuseGetCurrentSize(struct adapter *pAdapter, u8 efuseType, bool bPseudoTest); -int rtl8188e_Efuse_PgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest); -int rtl8188e_Efuse_PgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest); +void rtl8188e_EfusePowerSwitch(struct adapter *pAdapter, u8 PwrState); +void rtl8188e_ReadEFuse(struct adapter *Adapter, u16 _offset, u16 _size_byte, u8 *pbuf); void hal_notch_filter_8188e(struct adapter *adapter, bool enable); diff --git a/drivers/staging/r8188eu/include/ieee80211.h b/drivers/staging/r8188eu/include/ieee80211.h index 6c8206bd5466..3a23d5299314 100644 --- a/drivers/staging/r8188eu/include/ieee80211.h +++ b/drivers/staging/r8188eu/include/ieee80211.h @@ -1149,7 +1149,6 @@ void rtw_get_bcn_info(struct wlan_network *pnetwork); void rtw_macaddr_cfg(u8 *mac_addr); -u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, - unsigned char *MCS_rate); +u16 rtw_mcs_rate(u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char *MCS_rate); #endif /* IEEE80211_H */ diff --git a/drivers/staging/r8188eu/include/ieee80211_ext.h b/drivers/staging/r8188eu/include/ieee80211_ext.h deleted file mode 100644 index e7ade835d478..000000000000 --- a/drivers/staging/r8188eu/include/ieee80211_ext.h +++ /dev/null @@ -1,271 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. */ - -#ifndef __IEEE80211_EXT_H -#define __IEEE80211_EXT_H - -#include "osdep_service.h" -#include "drv_types.h" - -#define WMM_OUI_TYPE 2 -#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0 -#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1 -#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2 -#define WMM_VERSION 1 - -#define WPA_PROTO_WPA BIT(0) -#define WPA_PROTO_RSN BIT(1) - -#define WPA_KEY_MGMT_IEEE8021X BIT(0) -#define WPA_KEY_MGMT_PSK BIT(1) -#define WPA_KEY_MGMT_NONE BIT(2) -#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3) -#define WPA_KEY_MGMT_WPA_NONE BIT(4) - -#define WPA_CAPABILITY_PREAUTH BIT(0) -#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6) -#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9) - -#define PMKID_LEN 16 - -struct wpa_ie_hdr { - u8 elem_id; - u8 len; - u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ - u8 version[2]; /* little endian */ -} __packed; - -struct rsn_ie_hdr { - u8 elem_id; /* WLAN_EID_RSN */ - u8 len; - u8 version[2]; /* little endian */ -} __packed; - -struct wme_ac_parameter { -#if defined(__LITTLE_ENDIAN) - /* byte 1 */ - u8 aifsn:4, - acm:1, - aci:2, - reserved:1; - - /* byte 2 */ - u8 eCWmin:4, - eCWmax:4; -#elif defined(__BIG_ENDIAN) - /* byte 1 */ - u8 reserved:1, - aci:2, - acm:1, - aifsn:4; - - /* byte 2 */ - u8 eCWmax:4, - eCWmin:4; -#else -#error "Please fix <endian.h>" -#endif - - /* bytes 3 & 4 */ - u16 txopLimit; -} __packed; - -struct wme_parameter_element { - /* required fields for WME version 1 */ - u8 oui[3]; - u8 oui_type; - u8 oui_subtype; - u8 version; - u8 acInfo; - u8 reserved; - struct wme_ac_parameter ac[4]; - -} __packed; - -#define WPA_PUT_LE16(a, val) \ - do { \ - (a)[1] = ((u16) (val)) >> 8; \ - (a)[0] = ((u16) (val)) & 0xff; \ - } while (0) - -#define WPA_PUT_BE32(a, val) \ - do { \ - (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ - (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ - (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ - (a)[3] = (u8) (((u32) (val)) & 0xff); \ - } while (0) - -#define WPA_PUT_LE32(a, val) \ - do { \ - (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ - (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ - (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ - (a)[0] = (u8) (((u32) (val)) & 0xff); \ - } while (0) - -#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *)(a), (val)) - -/* Action category code */ -enum ieee80211_category { - WLAN_CATEGORY_SPECTRUM_MGMT = 0, - WLAN_CATEGORY_QOS = 1, - WLAN_CATEGORY_DLS = 2, - WLAN_CATEGORY_BACK = 3, - WLAN_CATEGORY_HT = 7, - WLAN_CATEGORY_WMM = 17, -}; - -/* SPECTRUM_MGMT action code */ -enum ieee80211_spectrum_mgmt_actioncode { - WLAN_ACTION_SPCT_MSR_REQ = 0, - WLAN_ACTION_SPCT_MSR_RPRT = 1, - WLAN_ACTION_SPCT_TPC_REQ = 2, - WLAN_ACTION_SPCT_TPC_RPRT = 3, - WLAN_ACTION_SPCT_CHL_SWITCH = 4, - WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, -}; - -/* BACK action code */ -enum ieee80211_back_actioncode { - WLAN_ACTION_ADDBA_REQ = 0, - WLAN_ACTION_ADDBA_RESP = 1, - WLAN_ACTION_DELBA = 2, -}; - -/* HT features action code */ -enum ieee80211_ht_actioncode { - WLAN_ACTION_NOTIFY_CH_WIDTH = 0, - WLAN_ACTION_SM_PS = 1, - WLAN_ACTION_PSPM = 2, - WLAN_ACTION_PCO_PHASE = 3, - WLAN_ACTION_MIMO_CSI_MX = 4, - WLAN_ACTION_MIMO_NONCP_BF = 5, - WLAN_ACTION_MIMP_CP_BF = 6, - WLAN_ACTION_ASEL_INDICATES_FB = 7, - WLAN_ACTION_HI_INFO_EXCHG = 8, -}; - -/* BACK (block-ack) parties */ -enum ieee80211_back_parties { - WLAN_BACK_RECIPIENT = 0, - WLAN_BACK_INITIATOR = 1, - WLAN_BACK_TIMER = 2, -}; - -struct ieee80211_mgmt { - u16 frame_control; - u16 duration; - u8 da[6]; - u8 sa[6]; - u8 bssid[6]; - u16 seq_ctrl; - union { - struct { - u16 auth_alg; - u16 auth_transaction; - u16 status_code; - /* possibly followed by Challenge text */ - u8 variable[0]; - } __packed auth; - struct { - u16 reason_code; - } __packed deauth; - struct { - u16 capab_info; - u16 listen_interval; - /* followed by SSID and Supported rates */ - u8 variable[0]; - } __packed assoc_req; - struct { - u16 capab_info; - u16 status_code; - u16 aid; - /* followed by Supported rates */ - u8 variable[0]; - } __packed assoc_resp, reassoc_resp; - struct { - u16 capab_info; - u16 listen_interval; - u8 current_ap[6]; - /* followed by SSID and Supported rates */ - u8 variable[0]; - } __packed reassoc_req; - struct { - u16 reason_code; - } __packed disassoc; - struct { - __le64 timestamp; - u16 beacon_int; - u16 capab_info; - /* followed by some of SSID, Supported rates, - * FH Params, DS Params, CF Params, IBSS Params, TIM */ - u8 variable[0]; - } __packed beacon; - struct { - /* only variable items: SSID, Supported rates */ - u8 variable[0]; - } __packed probe_req; - struct { - __le64 timestamp; - u16 beacon_int; - u16 capab_info; - /* followed by some of SSID, Supported rates, - * FH Params, DS Params, CF Params, IBSS Params */ - u8 variable[0]; - } __packed probe_resp; - struct { - u8 category; - union { - struct { - u8 action_code; - u8 dialog_token; - u8 status_code; - u8 variable[0]; - } __packed wme_action; - struct { - u8 action_code; - u8 dialog_token; - u16 capab; - u16 timeout; - u16 start_seq_num; - } __packed addba_req; - struct { - u8 action_code; - u8 dialog_token; - u16 status; - u16 capab; - u16 timeout; - } __packed addba_resp; - struct { - u8 action_code; - u16 params; - u16 reason_code; - } __packed delba; - structi { - u8 action_code; - /* capab_info for open and confirm, - * reason for close - */ - u16 aux; - /* Followed in plink_confirm by status - * code, AID and supported rates, - * and directly by supported rates in - * plink_open and plink_close - */ - u8 variable[0]; - } __packed plink_action; - struct{ - u8 action_code; - u8 variable[0]; - } __packed mesh_action; - } __packed u; - } __packed action; - } __packed u; -} __packed; - -/* mgmt header + 1 byte category code */ -#define IEEE80211_MIN_ACTION_SIZE \ - FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) - -#endif diff --git a/drivers/staging/r8188eu/include/odm.h b/drivers/staging/r8188eu/include/odm.h index f08655208b32..23a151c558dc 100644 --- a/drivers/staging/r8188eu/include/odm.h +++ b/drivers/staging/r8188eu/include/odm.h @@ -4,64 +4,30 @@ #ifndef __HALDMOUTSRC_H__ #define __HALDMOUTSRC_H__ -/* Add for AP/ADSLpseudo DM structuer requirement. */ -/* We need to remove to other position??? */ -struct rtl8192cd_priv { - u8 temp; -}; - struct rtw_dig { - u8 Dig_Enable_Flag; - u8 Dig_Ext_Port_Stage; - - int RssiLowThresh; - int RssiHighThresh; - - u32 FALowThresh; - u32 FAHighThresh; - - u8 CurSTAConnectState; - u8 PreSTAConnectState; - u8 CurMultiSTAConnectState; - u8 PreIGValue; u8 CurIGValue; u8 BackupIGValue; - s8 BackoffVal; - s8 BackoffVal_range_max; - s8 BackoffVal_range_min; u8 rx_gain_range_max; u8 rx_gain_range_min; - u8 Rssi_val_min; - u8 PreCCK_CCAThres; u8 CurCCK_CCAThres; - u8 PreCCKPDState; - u8 CurCCKPDState; u8 LargeFAHit; u8 ForbiddenIGI; u32 Recover_cnt; u8 DIG_Dynamic_MIN_0; - u8 DIG_Dynamic_MIN_1; bool bMediaConnect_0; - bool bMediaConnect_1; u32 AntDiv_RSSI_max; u32 RSSI_max; }; struct rtl_ps { - u8 pre_cca_state; - u8 cur_cca_state; - u8 pre_rf_state; u8 cur_rf_state; - - int rssi_val_min; - u8 initialize; u32 reg_874; u32 reg_c70; @@ -87,59 +53,11 @@ struct false_alarm_stats { u32 Cnt_BW_LSC; /* Gary */ }; -struct dyn_primary_cca { - u8 pri_cca_flag; - u8 intf_flag; - u8 intf_type; - u8 dup_rts_flag; - u8 monitor_flag; -}; - -struct rx_hpc { - u8 RXHP_flag; - u8 PSD_func_trigger; - u8 PSD_bitmap_RXHP[80]; - u8 Pre_IGI; - u8 Cur_IGI; - u8 Pre_pw_th; - u8 Cur_pw_th; - bool First_time_enter; - bool RXHP_enable; - u8 TP_Mode; - struct timer_list PSDTimer; -}; - #define ODM_ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ struct sw_ant_switch { - u8 try_flag; - s32 PreRSSI; u8 CurAntenna; - u8 PreAntenna; - u8 RSSI_Trying; - u8 TestMode; - u8 bTriggerAntennaSwitch; - u8 SelectAntennaMap; - u8 RSSI_target; - - /* Before link Antenna Switch check */ - u8 SWAS_NoLink_State; - u32 SWAS_NoLink_BK_Reg860; - - s32 RSSI_sum_A; - s32 RSSI_sum_B; - s32 RSSI_cnt_A; - s32 RSSI_cnt_B; - u64 lastTxOkCnt; - u64 lastRxOkCnt; - u64 TXByteCnt_A; - u64 TXByteCnt_B; - u64 RXByteCnt_A; - u64 RXByteCnt_B; - u8 TrafficLoad; - struct timer_list SwAntennaSwitchTimer; - u8 TxAnt[ODM_ASSOCIATE_ENTRY_NUM]; - u8 TargetSTA; + u8 SWAS_NoLink_State; /* Before link Antenna Switch check */ u8 RxIdleAnt; }; @@ -182,10 +100,6 @@ struct odm_per_pkt_info { bool bPacketBeacon; }; -struct odm_mac_status_info { - u8 test; -}; - enum odm_ability { /* BB Team */ ODM_DIG = 0x00000001, @@ -202,22 +116,6 @@ enum odm_ability { ODM_PSD2AFH = 0x00000800 }; -/* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ -/* Please declare below ODM relative info in your STA info structure. */ - -struct odm_sta_info { - /* Driver Write */ - bool bUsed; /* record the sta status link or not? */ - u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ - - /* ODM Write */ - /* 1 PHY_STATUS_INFO */ - u8 RSSI_Path[4]; /* */ - u8 RSSI_Ave; - u8 RXEVM[4]; - u8 RXSNR[4]; -}; - /* 2011/10/20 MH Define Common info enum for all team. */ enum odm_common_info_def { @@ -230,22 +128,16 @@ enum odm_common_info_def { /* Dynamic value: */ /* POINTER REFERENCE----------- */ - ODM_CMNINFO_TX_UNI, - ODM_CMNINFO_RX_UNI, ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ - ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ ODM_CMNINFO_BW, /* ODM_BW_E */ ODM_CMNINFO_CHNL, ODM_CMNINFO_SCAN, ODM_CMNINFO_POWER_SAVING, - ODM_CMNINFO_NET_CLOSED, /* POINTER REFERENCE----------- */ /* CALL BY VALUE------------- */ - ODM_CMNINFO_WIFI_DIRECT, - ODM_CMNINFO_WIFI_DISPLAY, ODM_CMNINFO_LINK, ODM_CMNINFO_RSSI_MIN, ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ @@ -256,27 +148,17 @@ enum odm_common_info_def { enum odm_ability_def { /* BB ODM section BIT 0-15 */ - ODM_BB_DIG = BIT(0), - ODM_BB_RA_MASK = BIT(1), - ODM_BB_DYNAMIC_TXPWR = BIT(2), ODM_BB_FA_CNT = BIT(3), ODM_BB_RSSI_MONITOR = BIT(4), ODM_BB_CCK_PD = BIT(5), ODM_BB_ANT_DIV = BIT(6), - ODM_BB_PWR_SAVE = BIT(7), ODM_BB_PWR_TRA = BIT(8), - ODM_BB_RATE_ADAPTIVE = BIT(9), - ODM_BB_PATH_DIV = BIT(10), - ODM_BB_PSD = BIT(11), - ODM_BB_RXHP = BIT(12), /* MAC DM section BIT 16-23 */ ODM_MAC_EDCA_TURBO = BIT(16), - ODM_MAC_EARLY_MODE = BIT(17), /* RF ODM section BIT 24-31 */ ODM_RF_TX_PWR_TRACK = BIT(24), - ODM_RF_RX_GAIN_TRACK = BIT(25), ODM_RF_CALIBRATION = BIT(26), }; @@ -424,15 +306,9 @@ struct odm_rf_cal { /* ODM Dynamic common info value definition */ struct fast_ant_train { - u8 Bssid[6]; u8 antsel_rx_keep_0; u8 antsel_rx_keep_1; u8 antsel_rx_keep_2; - u32 antSumRSSI[7]; - u32 antRSSIcnt[7]; - u32 antAveRSSI[7]; - u8 FAT_State; - u32 TrainIdx; u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; @@ -444,11 +320,6 @@ struct fast_ant_train { bool bBecomeLinked; }; -enum fat_state { - FAT_NORMAL_STATE = 0, - FAT_TRAINING_STATE = 1, -}; - enum ant_div_type { NO_ANTDIV = 0xFF, CG_TRX_HW_ANTDIV = 0x01, @@ -459,13 +330,7 @@ enum ant_div_type { /* Copy from SD4 defined structure. We use to support PHY DM integration. */ struct odm_dm_struct { - /* Add for different team use temporarily */ struct adapter *Adapter; /* For CE/NIC team */ - struct rtl8192cd_priv *priv; /* For AP/ADSL team */ - /* WHen you use above pointers, they must be initialized. */ - bool odm_ready; - - struct rtl8192cd_priv *fake_priv; /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ bool bCckHighPower; @@ -485,55 +350,25 @@ struct odm_dm_struct { /* Dynamic Value */ /* POINTER REFERENCE----------- */ - - u8 u8_temp; - bool bool_temp; - struct adapter *adapter_temp; - - /* TX Unicast byte count */ - u64 *pNumTxBytesUnicast; - /* RX Unicast byte count */ - u64 *pNumRxBytesUnicast; /* Wireless mode B/G/A/N = BIT(0)/BIT(1)/BIT(2)/BIT(3) */ u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ /* Secondary channel offset don't_care/below/above = 0/1/2 */ u8 *pSecChOffset; - /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ - u8 *pSecurity; /* BW info 20M/40M/80M = 0/1/2 */ u8 *pBandWidth; /* Central channel location Ch1/Ch2/.... */ u8 *pChannel; /* central channel number */ - /* Common info for 92D DMSP */ - bool *pbGetValueFromOtherMac; - struct adapter **pBuddyAdapter; - bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ /* Common info for Status */ bool *pbScanInProcess; bool *pbPowerSaving; - /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ - u8 *pOnePathCCA; - /* pMgntInfo->AntennaTest */ - u8 *pAntennaTest; - bool *pbNet_closed; /* POINTER REFERENCE----------- */ /* */ /* CALL BY VALUE------------- */ - bool bWIFI_Direct; - bool bWIFI_Display; bool bLinked; u8 RSSI_Min; - u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ bool bIsMPChip; bool bOneEntryOnly; - /* Common info for BTDM */ - bool bBtDisabled; /* BT is disabled */ - bool bBtHsOperation; /* BT HS mode is under progress */ - u8 btHsDigVal; /* use BT rssi to decide the DIG value */ - bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the - * EDCA Turbo */ - bool bBtBusy; /* BT is busy. */ /* CALL BY VALUE------------- */ /* 2 Define STA info. */ @@ -549,38 +384,16 @@ struct odm_dm_struct { /* Latest packet phy info (ODM write) */ struct odm_phy_dbg_info PhyDbgInfo; - /* Latest packet phy info (ODM write) */ - struct odm_mac_status_info *pMacInfo; - - /* Different Team independt structure?? */ - /* ODM Structure */ struct fast_ant_train DM_FatTable; struct rtw_dig DM_DigTable; struct rtl_ps DM_PSTable; - struct dyn_primary_cca DM_PriCCA; - struct rx_hpc DM_RXHP_Table; struct false_alarm_stats FalseAlmCnt; - struct false_alarm_stats FlaseAlmCntBuddyAdapter; struct sw_ant_switch DM_SWAT_Table; - bool RSSI_test; struct edca_turbo DM_EDCA_Table; - u32 WMMEDCA_BE; - /* Copy from SD4 structure */ - /* */ - /* ================================================== */ - /* */ - - bool *pbDriverStopped; - bool *pbDriverIsGoingToPnpSetPowerSleep; - bool *pinit_adpt_in_progress; /* PSD */ - bool bUserAssignLevel; - struct timer_list PSDTimer; - u8 RSSI_BT; /* come from BT */ - bool bPSDinProcess; bool bDMInitialGainEnable; struct odm_rate_adapt RateAdaptive; @@ -596,14 +409,7 @@ struct odm_dm_struct { u8 BbSwingIdxCckCurrent; u8 BbSwingIdxCckBase; bool BbSwingFlagCck; - /* ODM system resource. */ - - /* ODM relative time. */ - struct timer_list PathDivSwitchTimer; - /* 2011.09.27 add for Path Diversity */ - struct timer_list CCKPathDiversityTimer; - struct timer_list FastAntTrainingTimer; -}; /* DM_Dynamic_Mechanism_Structure */ +}; enum odm_bb_config_type { CONFIG_BB_PHY_REG, @@ -612,12 +418,6 @@ enum odm_bb_config_type { CONFIG_BB_PHY_REG_PG, }; -#define DM_DIG_THRESH_HIGH 40 -#define DM_DIG_THRESH_LOW 35 - -#define DM_false_ALARM_THRESH_LOW 400 -#define DM_false_ALARM_THRESH_HIGH 1000 - #define DM_DIG_MAX_NIC 0x4e #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ @@ -629,10 +429,6 @@ enum odm_bb_config_type { #define DM_DIG_FA_TH1 0x300/* 0x100 */ #define DM_DIG_FA_TH2 0x400/* 0x200 */ -#define DM_DIG_BACKOFF_MAX 12 -#define DM_DIG_BACKOFF_MIN -4 -#define DM_DIG_BACKOFF_DEFAULT 10 - /* 3=========================================================== */ /* 3 Rate Adaptive */ /* 3=========================================================== */ @@ -645,12 +441,6 @@ enum odm_bb_config_type { /* 3 BB Power Save */ /* 3=========================================================== */ -enum dm_1r_cca { - CCA_1R = 0, - CCA_2R = 1, - CCA_MAX = 2, -}; - enum dm_rf { RF_Save = 0, RF_Normal = 1, @@ -680,8 +470,6 @@ extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); -void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna); - void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); diff --git a/drivers/staging/r8188eu/include/odm_RTL8188E.h b/drivers/staging/r8188eu/include/odm_RTL8188E.h index 96e50c9224aa..3c6471f1a893 100644 --- a/drivers/staging/r8188eu/include/odm_RTL8188E.h +++ b/drivers/staging/r8188eu/include/odm_RTL8188E.h @@ -25,10 +25,4 @@ void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u8 antsel_tr_mux, void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm); -void odm_FastAntTrainingCallback(struct odm_dm_struct *pDM_Odm); - -void odm_FastAntTrainingWorkItemCallback(struct odm_dm_struct *pDM_Odm); - -void odm_PrimaryCCA_Init(struct odm_dm_struct *pDM_Odm); - #endif diff --git a/drivers/staging/r8188eu/include/odm_RegConfig8188E.h b/drivers/staging/r8188eu/include/odm_RegConfig8188E.h index 634454bffdb6..683fa4a07956 100644 --- a/drivers/staging/r8188eu/include/odm_RegConfig8188E.h +++ b/drivers/staging/r8188eu/include/odm_RegConfig8188E.h @@ -4,9 +4,6 @@ #ifndef __INC_ODM_REGCONFIG_H_8188E #define __INC_ODM_REGCONFIG_H_8188E -void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data, - enum rf_radio_path RF_PATH, u32 RegAddr); - void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data); diff --git a/drivers/staging/r8188eu/include/odm_interface.h b/drivers/staging/r8188eu/include/odm_interface.h deleted file mode 100644 index 17a315d19a50..000000000000 --- a/drivers/staging/r8188eu/include/odm_interface.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. */ - -#ifndef __ODM_INTERFACE_H__ -#define __ODM_INTERFACE_H__ - -enum odm_h2c_cmd { - ODM_H2C_RSSI_REPORT = 0, - ODM_H2C_PSD_RESULT= 1, - ODM_H2C_PathDiv = 2, - ODM_MAX_H2CCMD -}; - -/* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */ -/* Suggest HW team to use thread instead of workitem. Windows also support the feature. */ -typedef void (*RT_WORKITEM_CALL_BACK)(void *pContext); - -/* =========== Extern Variable ??? It should be forbidden. */ - -/* =========== EXtern Function Prototype */ - -u8 ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); - -u32 ODM_Read4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); - -void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u8 Data); - -void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data); - -void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 Data); - -void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, - u32 BitMask, u32 Data); - -u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); - -void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, - u32 BitMask, u32 Data); - -u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); - -void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum rf_radio_path eRFPath, - u32 RegAddr, u32 BitMask, u32 Data); - -u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum rf_radio_path eRFPath, - u32 RegAddr, u32 BitMask); - -/* Memory Relative Function. */ -s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, - u32 length); - -/* ODM Timer relative API. */ -void ODM_delay_ms(u32 ms); - -void ODM_delay_us(u32 us); - -void ODM_sleep_ms(u32 ms); - -#endif /* __ODM_INTERFACE_H__ */ diff --git a/drivers/staging/r8188eu/include/odm_precomp.h b/drivers/staging/r8188eu/include/odm_precomp.h deleted file mode 100644 index 22299f167af8..000000000000 --- a/drivers/staging/r8188eu/include/odm_precomp.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. i*/ - -#ifndef __ODM_PRECOMP_H__ -#define __ODM_PRECOMP_H__ - -#include "odm_types.h" - -#define TEST_FALG___ 1 - -/* 2 Config Flags and Structs - defined by each ODM Type */ - -#include "osdep_service.h" -#include "drv_types.h" -#include "hal_intf.h" - -/* 2 OutSrc Header Files */ - -#include "odm.h" -#include "odm_HWConfig.h" -#include "odm_RegDefine11N.h" - -#include "HalPhyRf_8188e.h"/* for IQK,LCK,Power-tracking */ -#include "Hal8188ERateAdaptive.h"/* for RA,Power training */ -#include "rtl8188e_hal.h" - -#include "odm_interface.h" - -#include "HalHWImg8188E_MAC.h" -#include "HalHWImg8188E_RF.h" -#include "HalHWImg8188E_BB.h" - -#include "odm_RegConfig8188E.h" -#include "odm_RTL8188E.h" - -void odm_DIGInit(struct odm_dm_struct *pDM_Odm); -void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm); -void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm); -void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm); -void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm); -void odm_SwAntDivInit_NIC(struct odm_dm_struct *pDM_Odm); -void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm); -void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm); -void odm_DIG(struct odm_dm_struct *pDM_Odm); -void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm); -void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm); -void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm); -void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm); -void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm); -void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm); -void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm); -void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm); - -#endif /* __ODM_PRECOMP_H__ */ diff --git a/drivers/staging/r8188eu/include/osdep_service.h b/drivers/staging/r8188eu/include/osdep_service.h index f6f5e4581212..6c8241372a06 100644 --- a/drivers/staging/r8188eu/include/osdep_service.h +++ b/drivers/staging/r8188eu/include/osdep_service.h @@ -74,38 +74,6 @@ static inline void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) #define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl #define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) -static inline void _init_workitem(struct work_struct *pwork, void *pfunc, void * cntx) -{ - INIT_WORK(pwork, pfunc); -} - -static inline void _set_workitem(struct work_struct *pwork) -{ - schedule_work(pwork); -} - -static inline void _cancel_workitem_sync(struct work_struct *pwork) -{ - cancel_work_sync(pwork); -} -/* */ -/* Global Mutex: can only be used at PASSIVE level. */ -/* */ - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\ - { \ - atomic_dec((atomic_t *)&(_MutexCounter)); \ - msleep(10); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - atomic_dec((atomic_t *)&(_MutexCounter)); \ -} - static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) { return netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && diff --git a/drivers/staging/r8188eu/include/rtl8188e_dm.h b/drivers/staging/r8188eu/include/rtl8188e_dm.h index 208bea050f6f..0b3a9a1a4e5c 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_dm.h +++ b/drivers/staging/r8188eu/include/rtl8188e_dm.h @@ -8,12 +8,7 @@ enum{ UP_LINK, DOWN_LINK, }; -/* duplicate code,will move to ODM ######### */ -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM 9 -#define HP_THERMAL_NUM 8 -/* duplicate code,will move to ODM ######### */ + struct dm_priv { u32 InitODMFlag; diff --git a/drivers/staging/r8188eu/include/rtl8188e_hal.h b/drivers/staging/r8188eu/include/rtl8188e_hal.h index d7db1dfc39d0..8134a173ea07 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_hal.h +++ b/drivers/staging/r8188eu/include/rtl8188e_hal.h @@ -13,11 +13,18 @@ #include "rtl8188e_recv.h" #include "rtl8188e_xmit.h" #include "rtl8188e_cmd.h" -#include "Hal8188EPwrSeq.h" -#include "rtl8188e_sreset.h" #include "rtw_efuse.h" - -#include "odm_precomp.h" +#include "odm_types.h" +#include "odm.h" +#include "odm_HWConfig.h" +#include "odm_RegDefine11N.h" +#include "HalPhyRf_8188e.h" +#include "Hal8188ERateAdaptive.h" +#include "HalHWImg8188E_MAC.h" +#include "HalHWImg8188E_RF.h" +#include "HalHWImg8188E_BB.h" +#include "odm_RegConfig8188E.h" +#include "odm_RTL8188E.h" /* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */ #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow @@ -168,42 +175,15 @@ struct hal_data_8188e { u16 BasicRateSet; - /* rf_ctrl */ - u8 rf_chip; - u8 rf_type; - - u8 BoardType; - - /* EEPROM setting. */ - u16 EEPROMVID; - u16 EEPROMPID; - u16 EEPROMSVID; - u16 EEPROMSDID; - u8 EEPROMCustomerID; - u8 EEPROMSubCustomerID; - u8 EEPROMVersion; u8 EEPROMRegulatory; - - u8 bTXPowerDataReadFromEEPORM; u8 EEPROMThermalMeter; - u8 bAPKThermalMeterIgnore; - - bool EepromOrEfuse; - struct efuse_hal EfuseHal; - u8 Index24G_CCK_Base[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - u8 Index24G_BW40_Base[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + u8 Index24G_CCK_Base[CHANNEL_MAX_NUMBER]; + u8 Index24G_BW40_Base[CHANNEL_MAX_NUMBER]; /* If only one tx, only BW20 and OFDM are used. */ - s8 CCK_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT]; - s8 OFDM_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT]; - s8 BW20_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT]; - s8 BW40_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT]; - - u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - /* For HT 40MHZ pwr */ - u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - /* For HT 40MHZ pwr */ - u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + s8 OFDM_24G_Diff[MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_TX_COUNT]; + /* HT 20<->40 Pwr diff */ u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT<->legacy pwr diff */ @@ -212,7 +192,6 @@ struct hal_data_8188e { u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ /* The current Tx Power Level */ u8 CurrentCckTxPwrIdx; u8 CurrentOfdm24GTxPwrIdx; @@ -220,32 +199,18 @@ struct hal_data_8188e { u8 CurrentBW4024GTxPwrIdx; /* Read/write are allow for following hardware information variables */ - u8 framesync; - u32 framesyncC34; - u8 framesyncMonitor; - u8 DefaultInitialGain[4]; u8 pwrGroupCnt; u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; - u32 CCKTxPowerLevelOriginalOffset; u8 CrystalCap; - u32 AntennaTxPath; /* Antenna path Tx */ - u32 AntennaRxPath; /* Antenna path Rx */ u8 ExternalPA; - u8 bLedOpenDrain; /* Open-drain support for controlling the LED.*/ - - u8 b1x1RecvCombine; /* for 1T1R receive combining */ - u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ - struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */ + struct bb_reg_def PHYRegDef[2]; /* Radio A/B */ u32 RfRegChnlVal[2]; - /* RDG enable */ - bool bRDGEnable; - /* for host message to fw */ u8 LastHMEBoxNum; @@ -263,26 +228,10 @@ struct hal_data_8188e { u8 bDumpRxPkt;/* for debug */ u8 bDumpTxPkt;/* for debug */ - u8 FwRsvdPageStartOffset; /* Reserve page start offset except - * beacon in TxQ. */ - - /* 2010/08/09 MH Add CU power down mode. */ - bool pwrdown; - - /* Add for dual MAC 0--Mac0 1--Mac1 */ - u32 interfaceIndex; u8 OutEpQueueSel; u8 OutEpNumber; - /* Add for USB aggreation mode dynamic shceme. */ - bool UsbRxHighSpeedMode; - - /* 2010/11/22 MH Add for slim combo debug mode selective. */ - /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. - * HW auto suspend ability. Close BT clock. */ - bool SlimComboDbg; - u16 EfuseUsedBytes; struct P2P_PS_Offload_t p2p_ps_offload; @@ -293,12 +242,8 @@ struct hal_data_8188e { u32 UsbBulkOutSize; - /* Interrupt relatd register information. */ - u32 IntArray[3];/* HISR0,HISR1,HSISR */ - u8 C2hArray[16]; u8 UsbTxAggMode; u8 UsbTxAggDescNum; - u32 MaxUsbRxAggBlock; enum usb_rx_agg_mode UsbRxAggMode; u8 UsbRxAggBlockCount; /* USB Block count. Block size is @@ -309,9 +254,6 @@ struct hal_data_8188e { u8 UsbRxAggPageTimeout; }; -#define GET_HAL_DATA(__pAdapter) \ - ((struct hal_data_8188e *)((__pAdapter)->HalData)) - /* rtl8188e_hal_init.c */ s32 rtl8188e_FirmwareDownload(struct adapter *padapter); void _8051Reset88E(struct adapter *padapter); @@ -321,25 +263,18 @@ s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); /* EFuse */ u8 GetEEPROMSize8188E(struct adapter *padapter); -void Hal_InitPGData88E(struct adapter *padapter); void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail); -void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, - bool AutoLoadFail); void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail); -void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, - bool AutoLoadFail); void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent, bool AutoLoadFail); void Hal_ReadThermalMeter_88E(struct adapter * dapter, u8 *PROMContent, bool AutoloadFail); void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail); -void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, - bool AutoLoadFail); void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail); @@ -347,6 +282,5 @@ void rtl8188e_read_chip_version(struct adapter *padapter); s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); void rtw_cancel_all_timer(struct adapter *padapter); -void _ps_open_RF(struct adapter *adapt); #endif /* __RTL8188E_HAL_H__ */ diff --git a/drivers/staging/r8188eu/include/rtl8188e_led.h b/drivers/staging/r8188eu/include/rtl8188e_led.h deleted file mode 100644 index 02cdc970bb17..000000000000 --- a/drivers/staging/r8188eu/include/rtl8188e_led.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. */ - -#ifndef __RTL8188E_LED_H__ -#define __RTL8188E_LED_H__ - -#include "osdep_service.h" -#include "drv_types.h" - -/* */ -/* Interface to manipulate LED objects. */ -/* */ -void rtl8188eu_InitSwLeds(struct adapter *padapter); -void rtl8188eu_DeInitSwLeds(struct adapter *padapter); - -#endif diff --git a/drivers/staging/r8188eu/include/rtl8188e_recv.h b/drivers/staging/r8188eu/include/rtl8188e_recv.h index 2ab395ef579b..0be9896eaf0f 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_recv.h +++ b/drivers/staging/r8188eu/include/rtl8188e_recv.h @@ -9,8 +9,6 @@ #define RECV_BLK_SZ 512 #define RECV_BLK_CNT 16 #define RECV_BLK_TH RECV_BLK_CNT -#define RECV_BULK_IN_ADDR 0x80 -#define RECV_INT_IN_ADDR 0x81 #define NR_PREALLOC_RECV_SKB (8) @@ -39,7 +37,6 @@ enum rx_packet_type { HIS_REPORT,/* USB HISR RPT */ }; -#define INTERRUPT_MSG_FORMAT_LEN 60 void rtl8188eu_init_recvbuf(struct recv_buf *buf); s32 rtl8188eu_init_recv_priv(struct adapter *padapter); void rtl8188eu_free_recv_priv(struct adapter * padapter); diff --git a/drivers/staging/r8188eu/include/rtl8188e_spec.h b/drivers/staging/r8188eu/include/rtl8188e_spec.h index 01aeaa4ac605..009222b4a95d 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_spec.h +++ b/drivers/staging/r8188eu/include/rtl8188e_spec.h @@ -475,13 +475,6 @@ Default: 00b. #define MSR_INFRA 0x02 #define MSR_AP 0x03 -/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ -#define USB_INTR_CONTENT_C2H_OFFSET 0 -#define USB_INTR_CONTENT_CPWM1_OFFSET 16 -#define USB_INTR_CONTENT_CPWM2_OFFSET 20 -#define USB_INTR_CONTENT_HISR_OFFSET 48 -#define USB_INTR_CONTENT_HISRE_OFFSET 52 - /* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ /* IOL config for REG_FDHM0(Reg0x88) */ #define CMD_INIT_LLT BIT(0) @@ -1283,53 +1276,15 @@ Current IOREG MAP #define EEPROM_RF_BOARD_OPTION_88E 0xC1 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 -#define EEPROM_RF_BT_SETTING_88E 0xC3 -#define EEPROM_VERSION_88E 0xC4 -#define EEPROM_CUSTOMERID_88E 0xC5 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9 -/* RTL88EE */ -#define EEPROM_MAC_ADDR_88EE 0xD0 -#define EEPROM_VID_88EE 0xD6 -#define EEPROM_DID_88EE 0xD8 -#define EEPROM_SVID_88EE 0xDA -#define EEPROM_SMID_88EE 0xDC - /* RTL88EU */ #define EEPROM_MAC_ADDR_88EU 0xD7 -#define EEPROM_VID_88EU 0xD0 -#define EEPROM_PID_88EU 0xD2 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 /* RTL88ES */ #define EEPROM_MAC_ADDR_88ES 0x11A -/* EEPROM/Efuse Value Type */ -#define EETYPE_TX_PWR 0x0 - -/* Default Value for EEPROM or EFUSE!!! */ -#define EEPROM_Default_TSSI 0x0 -#define EEPROM_Default_TxPowerDiff 0x0 -#define EEPROM_Default_CrystalCap 0x5 -/* Default: 2X2, RTL8192CE(QFPN68) */ -#define EEPROM_Default_BoardType 0x02 -#define EEPROM_Default_TxPower 0x1010 -#define EEPROM_Default_HT2T_TxPwr 0x10 - -#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 -#define EEPROM_Default_ThermalMeter 0x12 - -#define EEPROM_Default_AntTxPowerDiff 0x0 -#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 -#define EEPROM_Default_TxPowerLevel 0x2A - -#define EEPROM_Default_HT40_2SDiff 0x0 -/* HT20<->40 default Tx Power Index Difference */ -#define EEPROM_Default_HT20_Diff 2 -#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 -#define EEPROM_Default_HT40_PwrMaxOffset 0 -#define EEPROM_Default_HT20_PwrMaxOffset 0 - #define EEPROM_Default_CrystalCap_88E 0x20 #define EEPROM_Default_ThermalMeter_88E 0x18 @@ -1339,18 +1294,7 @@ Current IOREG MAP #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 #define EEPROM_DEFAULT_DIFF 0XFE -#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F #define EEPROM_DEFAULT_BOARD_OPTION 0x00 -#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 -#define EEPROM_DEFAULT_BT_OPTION 0x10 - -/* For debug */ -#define EEPROM_Default_PID 0x1234 -#define EEPROM_Default_VID 0x5678 -#define EEPROM_Default_CustomerID 0xAB -#define EEPROM_Default_CustomerID_8188E 0x00 -#define EEPROM_Default_SubCustomerID 0xCD -#define EEPROM_Default_Version 0 #define EEPROM_CHANNEL_PLAN_FCC 0x0 #define EEPROM_CHANNEL_PLAN_IC 0x1 @@ -1367,11 +1311,6 @@ Current IOREG MAP #define EEPROM_USB_OPTIONAL1 0xE #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_TOSHIBA 0x4 -#define EEPROM_CID_CCX 0x10 /* CCX test. */ -#define EEPROM_CID_QMI 0x0D -#define EEPROM_CID_WHQL 0xFE #define RTL_EEPROM_ID 0x8129 #endif /* __RTL8188E_SPEC_H__ */ diff --git a/drivers/staging/r8188eu/include/rtl8188e_sreset.h b/drivers/staging/r8188eu/include/rtl8188e_sreset.h deleted file mode 100644 index bb8b0048fbf9..000000000000 --- a/drivers/staging/r8188eu/include/rtl8188e_sreset.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. */ - -#ifndef _RTL8188E_SRESET_H_ -#define _RTL8188E_SRESET_H_ - -#include "osdep_service.h" -#include "drv_types.h" - -void rtl8188e_sreset_xmit_status_check(struct adapter *padapter); -void rtl8188e_sreset_linked_status_check(struct adapter *padapter); - -#endif diff --git a/drivers/staging/r8188eu/include/rtw_cmd.h b/drivers/staging/r8188eu/include/rtw_cmd.h index 47c3c80cc24a..cf0945ae11c1 100644 --- a/drivers/staging/r8188eu/include/rtw_cmd.h +++ b/drivers/staging/r8188eu/include/rtw_cmd.h @@ -42,7 +42,6 @@ struct cmd_priv { u8 *cmd_allocated_buf; u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ u8 *rsp_allocated_buf; - u32 cmd_issued_cnt; u32 cmd_done_cnt; u32 rsp_cnt; u8 cmdthd_running; diff --git a/drivers/staging/r8188eu/include/rtw_debug.h b/drivers/staging/r8188eu/include/rtw_debug.h index 0a77e3e73a45..311051757715 100644 --- a/drivers/staging/r8188eu/include/rtw_debug.h +++ b/drivers/staging/r8188eu/include/rtw_debug.h @@ -54,22 +54,10 @@ extern u32 GlobalDebugLevel; -#define DBG_88E_LEVEL(_level, fmt, arg...) \ - do { \ - if (_level <= GlobalDebugLevel) \ - pr_info(DRIVER_PREFIX"INFO " fmt, ##arg); \ - } while (0) - #define DBG_88E(...) \ do { \ if (_drv_err_ <= GlobalDebugLevel) \ pr_info(DRIVER_PREFIX __VA_ARGS__); \ } while (0) -#define MSG_88E(...) \ - do { \ - if (_drv_err_ <= GlobalDebugLevel) \ - pr_info(DRIVER_PREFIX __VA_ARGS__); \ - } while (0) - #endif /* __RTW_DEBUG_H__ */ diff --git a/drivers/staging/r8188eu/include/rtw_eeprom.h b/drivers/staging/r8188eu/include/rtw_eeprom.h index e517239bd75e..3e8d3bb48903 100644 --- a/drivers/staging/r8188eu/include/rtw_eeprom.h +++ b/drivers/staging/r8188eu/include/rtw_eeprom.h @@ -7,38 +7,7 @@ #include "osdep_service.h" #include "drv_types.h" -#define RTL8712_EEPROM_ID 0x8712 - #define HWSET_MAX_SIZE_512 512 -#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 - -#define CLOCK_RATE 50 /* 100us */ - -/* EEPROM opcodes */ -#define EEPROM_READ_OPCODE 06 -#define EEPROM_WRITE_OPCODE 05 -#define EEPROM_ERASE_OPCODE 07 -#define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */ -#define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ - -/* Country codes */ -#define USA 0x555320 -#define EUROPE 0x1 /* temp, should be provided later */ -#define JAPAN 0x2 /* temp, should be provided later */ - -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_ALPHA 0x1 -#define EEPROM_CID_Senao 0x3 -#define EEPROM_CID_NetCore 0x5 -#define EEPROM_CID_CAMEO 0X8 -#define EEPROM_CID_SITECOM 0x9 -#define EEPROM_CID_COREGA 0xB -#define EEPROM_CID_EDIMAX_BELK 0xC -#define EEPROM_CID_SERCOMM_BELK 0xE -#define EEPROM_CID_CAMEO1 0xF -#define EEPROM_CID_WNC_COREGA 0x12 -#define EEPROM_CID_CLEVO 0x13 -#define EEPROM_CID_WHQL 0xFE struct eeprom_priv { u8 bautoload_fail_flag; diff --git a/drivers/staging/r8188eu/include/rtw_efuse.h b/drivers/staging/r8188eu/include/rtw_efuse.h index 2e19b7be1075..2daf69f554d5 100644 --- a/drivers/staging/r8188eu/include/rtw_efuse.h +++ b/drivers/staging/r8188eu/include/rtw_efuse.h @@ -4,110 +4,10 @@ #ifndef __RTW_EFUSE_H__ #define __RTW_EFUSE_H__ -#include "osdep_service.h" - -#define EFUSE_ERROE_HANDLE 1 - -#define PG_STATE_HEADER 0x01 -#define PG_STATE_WORD_0 0x02 -#define PG_STATE_WORD_1 0x04 -#define PG_STATE_WORD_2 0x08 -#define PG_STATE_WORD_3 0x10 -#define PG_STATE_DATA 0x20 - -#define PG_SWBYTE_H 0x01 -#define PG_SWBYTE_L 0x02 - -#define PGPKT_DATA_SIZE 8 - -#define EFUSE_WIFI 0 -#define EFUSE_BT 1 - -enum _EFUSE_DEF_TYPE { - TYPE_EFUSE_MAX_SECTION = 0, - TYPE_EFUSE_REAL_CONTENT_LEN = 1, - TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, - TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, - TYPE_EFUSE_MAP_LEN = 4, - TYPE_EFUSE_PROTECT_BYTES_BANK = 5, - TYPE_EFUSE_CONTENT_LEN_BANK = 6, -}; - -/* E-Fuse */ -#define EFUSE_MAP_SIZE 512 -#define EFUSE_MAX_SIZE 256 -/* end of E-Fuse */ - -#define EFUSE_MAX_MAP_LEN 512 -#define EFUSE_MAX_HW_SIZE 512 -#define EFUSE_MAX_SECTION_BASE 16 - -#define EXT_HEADER(header) ((header & 0x1F) == 0x0F) -#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) -#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5) - -#define EFUSE_REPEAT_THRESHOLD_ 3 - -/* The following is for BT Efuse definition */ -#define EFUSE_BT_MAX_MAP_LEN 1024 -#define EFUSE_MAX_BANK 4 -#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) -/*--------------------------Define Parameters-------------------------------*/ #define EFUSE_MAX_WORD_UNIT 4 -/*------------------------------Define structure----------------------------*/ -struct pgpkt { - u8 offset; - u8 word_en; - u8 data[8]; - u8 word_cnts; -}; - -/*------------------------------Define structure----------------------------*/ -struct efuse_hal { - u8 fakeEfuseBank; - u32 fakeEfuseUsedBytes; - u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; - u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; - u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; - - u16 BTEfuseUsedBytes; - u8 BTEfuseUsedPercentage; - u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; - u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; - u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; - - u16 fakeBTEfuseUsedBytes; - u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; - u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; - u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; -}; - -/*------------------------Export global variable----------------------------*/ -extern u8 fakeEfuseBank; -extern u32 fakeEfuseUsedBytes; -extern u8 fakeEfuseContent[]; -extern u8 fakeEfuseInitMap[]; -extern u8 fakeEfuseModifiedMap[]; - -extern u32 BTEfuseUsedBytes; -extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; -extern u8 BTEfuseInitMap[]; -extern u8 BTEfuseModifiedMap[]; - -extern u32 fakeBTEfuseUsedBytes; -extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; -extern u8 fakeBTEfuseInitMap[]; -extern u8 fakeBTEfuseModifiedMap[]; -/*------------------------Export global variable----------------------------*/ - -u8 Efuse_CalculateWordCnts(u8 word_en); -void ReadEFuseByte(struct adapter *adapter, u16 _offset, u8 *pbuf, bool test); -u8 efuse_OneByteRead(struct adapter *adapter, u16 addr, u8 *data, bool test); -u8 efuse_OneByteWrite(struct adapter *adapter, u16 addr, u8 data, bool test); - -void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); +void ReadEFuseByte(struct adapter *adapter, u16 _offset, u8 *pbuf); -void EFUSE_ShadowMapUpdate(struct adapter *adapter, u8 efusetype, bool test); +void EFUSE_ShadowMapUpdate(struct adapter *adapter); #endif diff --git a/drivers/staging/r8188eu/include/rtw_io.h b/drivers/staging/r8188eu/include/rtw_io.h index c6a078210eeb..6910e2b430e2 100644 --- a/drivers/staging/r8188eu/include/rtw_io.h +++ b/drivers/staging/r8188eu/include/rtw_io.h @@ -224,7 +224,7 @@ u8 rtw_read8(struct adapter *adapter, u32 addr); u16 rtw_read16(struct adapter *adapter, u32 addr); u32 rtw_read32(struct adapter *adapter, u32 addr); void _rtw_read_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -u32 rtw_read_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +u32 rtw_read_port(struct adapter *adapter, u8 *pmem); void rtw_read_port_cancel(struct adapter *adapter); int rtw_write8(struct adapter *adapter, u32 addr, u8 val); diff --git a/drivers/staging/r8188eu/include/rtw_led.h b/drivers/staging/r8188eu/include/rtw_led.h index c035fe267635..2c14cb23d9ad 100644 --- a/drivers/staging/r8188eu/include/rtw_led.h +++ b/drivers/staging/r8188eu/include/rtw_led.h @@ -7,41 +7,7 @@ #include "osdep_service.h" #include "drv_types.h" -#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) - -#define LED_BLINK_NORMAL_INTERVAL 100 -#define LED_BLINK_SLOWLY_INTERVAL 200 -#define LED_BLINK_LONG_INTERVAL 400 - -#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 -#define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */ -#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */ -#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 -#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 - -#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 -#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 - -#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 -#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 - -#define LED_BLINK_FAST_INTERVAL_BITLAND 30 - -/* 060403, rcnjko: Customized for AzWave. */ -#define LED_CM2_BLINK_ON_INTERVAL 250 -#define LED_CM2_BLINK_OFF_INTERVAL 4750 - -#define LED_CM8_BLINK_INTERVAL 500 /* for QMI */ -#define LED_CM8_BLINK_OFF_INTERVAL 3750 /* for QMI */ - -/* 080124, lanhsin: Customized for RunTop */ -#define LED_RunTop_BLINK_INTERVAL 300 - -/* 060421, rcnjko: Customized for Sercomm Printer Server case. */ -#define LED_CM3_BLINK_INTERVAL 1500 - enum LED_CTL_MODE { - LED_CTL_POWER_ON = 1, LED_CTL_LINK = 2, LED_CTL_NO_LINK = 3, LED_CTL_TX = 4, @@ -51,10 +17,7 @@ enum LED_CTL_MODE { LED_CTL_START_TO_LINK = 8, LED_CTL_START_WPS = 9, LED_CTL_STOP_WPS = 10, - LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */ - LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */ - LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */ - LED_CTL_CONNECTION_NO_TRANSFER = 14, + LED_CTL_STOP_WPS_FAIL = 12, }; enum LED_STATE_871x { @@ -63,99 +26,46 @@ enum LED_STATE_871x { RTW_LED_OFF = 2, LED_BLINK_NORMAL = 3, LED_BLINK_SLOWLY = 4, - LED_BLINK_POWER_ON = 5, LED_BLINK_SCAN = 6, /* LED is blinking during scanning period, * the # of times to blink is depend on time * for scanning. */ - LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */ LED_BLINK_StartToBlink = 8,/* Customzied for Sercomm Printer * Server case */ LED_BLINK_TXRX = 9, LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */ - LED_BLINK_WPS_STOP = 11, /* for ALPHA */ - LED_BLINK_WPS_STOP_OVERLAP = 12, /* for BELKIN */ + LED_BLINK_WPS_STOP = 11, LED_BLINK_RUNTOP = 13, /* Customized for RunTop */ - LED_BLINK_CAMEO = 14, - LED_BLINK_XAVI = 15, - LED_BLINK_ALWAYS_ON = 16, -}; - -enum LED_PIN_871x { - LED_PIN_NULL = 0, - LED_PIN_LED0 = 1, - LED_PIN_LED1 = 2, - LED_PIN_LED2 = 3, - LED_PIN_GPIO0 = 4, }; struct LED_871x { struct adapter *padapter; - enum LED_PIN_871x LedPin; /* Identify how to implement this - * SW led. */ enum LED_STATE_871x CurrLedState; /* Current LED state. */ enum LED_STATE_871x BlinkingLedState; /* Next state for blinking, * either RTW_LED_ON or RTW_LED_OFF are. */ - u8 bLedOn; /* true if LED is ON, false if LED is OFF. */ + bool bLedOn; /* true if LED is ON, false if LED is OFF. */ - u8 bLedBlinkInProgress; /* true if it is blinking, false o.w.. */ + bool bLedBlinkInProgress; /* true if it is blinking, false o.w.. */ - u8 bLedWPSBlinkInProgress; + bool bLedWPSBlinkInProgress; u32 BlinkTimes; /* Number of times to toggle led state for blinking. */ - struct timer_list BlinkTimer; /* Timer object for led blinking. */ - - /* ALPHA, added by chiyoko, 20090106 */ - u8 bLedNoLinkBlinkInProgress; - u8 bLedLinkBlinkInProgress; - u8 bLedStartToLinkBlinkInProgress; - u8 bLedScanBlinkInProgress; - struct work_struct BlinkWorkItem; /* Workitem used by BlinkTimer to - * manipulate H/W to blink LED. */ + bool bLedNoLinkBlinkInProgress; + bool bLedLinkBlinkInProgress; + bool bLedScanBlinkInProgress; + struct delayed_work blink_work; }; -#define IS_LED_WPS_BLINKING(_LED_871x) \ - (((struct LED_871x *)_LED_871x)->CurrLedState == LED_BLINK_WPS || \ - ((struct LED_871x *)_LED_871x)->CurrLedState == LED_BLINK_WPS_STOP || \ - ((struct LED_871x *)_LED_871x)->bLedWPSBlinkInProgress) - -#define IS_LED_BLINKING(_LED_871x) \ - (((struct LED_871x *)_LED_871x)->bLedWPSBlinkInProgress || \ - ((struct LED_871x *)_LED_871x)->bLedScanBlinkInProgress) - -void LedControl8188eu(struct adapter *padapter, enum LED_CTL_MODE LedAction); - struct led_priv{ - /* add for led control */ struct LED_871x SwLed0; - struct LED_871x SwLed1; - u8 bRegUseLed; - void (*LedControlHandler)(struct adapter *padapter, - enum LED_CTL_MODE LedAction); - /* add for led control */ + bool bRegUseLed; }; -#define rtw_led_control(adapt, action) \ - do { \ - if ((adapt)->ledpriv.LedControlHandler) \ - (adapt)->ledpriv.LedControlHandler((adapt), (action)); \ - } while (0) - -void BlinkTimerCallback(struct timer_list *t); -void BlinkWorkItemCallback(struct work_struct *work); - -void ResetLedStatus(struct LED_871x * pLed); - -void InitLed871x(struct adapter *padapter, struct LED_871x *pLed, - enum LED_PIN_871x LedPin); - -void DeInitLed871x(struct LED_871x *pLed); +void rtl8188eu_InitSwLeds(struct adapter *padapter); +void rtl8188eu_DeInitSwLeds(struct adapter *padapter); -/* hal... */ -void BlinkHandler(struct LED_871x * pLed); -void SwLedOn(struct adapter *padapter, struct LED_871x *pLed); -void SwLedOff(struct adapter *padapter, struct LED_871x *pLed); +void rtw_led_control(struct adapter *padapter, enum LED_CTL_MODE LedAction); #endif /* __RTW_LED_H_ */ diff --git a/drivers/staging/r8188eu/include/rtw_mlme.h b/drivers/staging/r8188eu/include/rtw_mlme.h index e8d51f495702..77169c15080a 100644 --- a/drivers/staging/r8188eu/include/rtw_mlme.h +++ b/drivers/staging/r8188eu/include/rtw_mlme.h @@ -243,18 +243,6 @@ struct wifidirect_info { * by using the sta_preset CAPI. */ /* 0: disable */ /* 1: enable */ - u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma*/ - /* 0: disable */ - /* 1: enable */ - u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security - * function for TDLS by WFD Sigma */ - /* 0: disable */ - /* In this case, the driver can't issue the tdsl - * setup request frame. */ - /* 1: enable */ - /* In this case, the driver can issue the tdls - * setup request frame */ - /* even the current security is weak security. */ /* This field will store the WPS value (PIN value or PBC) that UI had * got from the user. */ diff --git a/drivers/staging/r8188eu/include/rtw_mlme_ext.h b/drivers/staging/r8188eu/include/rtw_mlme_ext.h index 5b307ad3afa5..26f31f20e428 100644 --- a/drivers/staging/r8188eu/include/rtw_mlme_ext.h +++ b/drivers/staging/r8188eu/include/rtw_mlme_ext.h @@ -162,11 +162,6 @@ struct rt_channel_plan { unsigned char Len; }; -struct rt_channel_plan_2g { - unsigned char Channel[MAX_CHANNEL_NUM_2G]; - unsigned char Len; -}; - struct rt_channel_plan_map { unsigned char Index2G; }; diff --git a/drivers/staging/r8188eu/include/rtw_pwrctrl.h b/drivers/staging/r8188eu/include/rtw_pwrctrl.h index b19ef796ab54..2d5298373d74 100644 --- a/drivers/staging/r8188eu/include/rtw_pwrctrl.h +++ b/drivers/staging/r8188eu/include/rtw_pwrctrl.h @@ -19,10 +19,6 @@ enum power_mgnt { PS_MODE_DTIM, PS_MODE_VOIP, PS_MODE_UAPSD_WMM, - PS_MODE_UAPSD, - PS_MODE_IBSS, - PS_MODE_WWLAN, - PM_Radio_Off, PM_Card_Disable, PS_MODE_NUM }; @@ -57,7 +53,6 @@ struct pwrctrl_priv { u8 reg_rfoff; u8 reg_pdnmode; /* powerdown mode */ - u32 rfoff_reason; /* RF OFF Level */ u32 cur_ps_level; @@ -80,7 +75,6 @@ struct pwrctrl_priv { s32 pnp_current_pwr_state; u8 pnp_bstop_trx; - u8 bInternalAutoSuspend; u8 bInSuspend; u8 bSupportRemoteWakeup; struct timer_list pwr_state_check_timer; @@ -93,7 +87,6 @@ struct pwrctrl_priv { enum rt_rf_power_state change_rfpwrstate; u8 wepkeymask; - u8 bHWPowerdown;/* if support hw power down */ u8 bkeepfwalive; }; diff --git a/drivers/staging/r8188eu/include/rtw_recv.h b/drivers/staging/r8188eu/include/rtw_recv.h index 1e28ec731547..b43a46887343 100644 --- a/drivers/staging/r8188eu/include/rtw_recv.h +++ b/drivers/staging/r8188eu/include/rtw_recv.h @@ -177,7 +177,6 @@ struct recv_priv { uint rx_smallpacket_crcerr; uint rx_middlepacket_crcerr; struct semaphore allrxreturnevt; - uint ff_hwaddr; u8 rx_pending_cnt; struct tasklet_struct irq_prepare_beacon_tasklet; diff --git a/drivers/staging/r8188eu/include/rtw_rf.h b/drivers/staging/r8188eu/include/rtw_rf.h index 7ec252fec054..b7267e75346c 100644 --- a/drivers/staging/r8188eu/include/rtw_rf.h +++ b/drivers/staging/r8188eu/include/rtw_rf.h @@ -6,33 +6,16 @@ #include "rtw_cmd.h" -#define OFDM_PHY 1 -#define MIXED_PHY 2 -#define CCK_PHY 3 - #define NumRates (13) /* slot time for 11g */ #define SHORT_SLOT_TIME 9 #define NON_SHORT_SLOT_TIME 20 -#define RTL8711_RF_MAX_SENS 6 -#define RTL8711_RF_DEF_SENS 4 - -/* We now define the following channels as the max channels in each - * channel plan. */ -/* 2G, total 14 chnls */ -/* {1,2,3,4,5,6,7,8,9,10,11,12,13,14} */ -#define MAX_CHANNEL_NUM_2G 14 #define MAX_CHANNEL_NUM 14 /* 2.4 GHz only */ #define NUM_REGULATORYS 1 -/* Country codes */ -#define USA 0x555320 -#define EUROPE 0x1 /* temp, should be provided later */ -#define JAPAN 0x2 /* temp, should be provided later */ - struct regulatory_class { u32 starting_freq; /* MHz, */ u8 channel_set[MAX_CHANNEL_NUM]; @@ -69,13 +52,6 @@ enum _REG_PREAMBLE_MODE { PREAMBLE_SHORT = 3, }; -enum rf90_radio_path { - RF90_PATH_A = 0, /* Radio Path A */ - RF90_PATH_B = 1, /* Radio Path B */ - RF90_PATH_C = 2, /* Radio Path C */ - RF90_PATH_D = 3 /* Radio Path D */ -}; - /* Bandwidth Offset */ #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 @@ -99,16 +75,6 @@ enum ht_extchnl_offset { HT_EXTCHNL_OFFSET_LOWER = 3, }; -/* 2007/11/15 MH Define different RF type. */ -enum rt_rf_type_def { - RF_1T2R = 0, - RF_2T4R = 1, - RF_2T2R = 2, - RF_1T1R = 3, - RF_2T2R_GREEN = 4, - RF_819X_MAX_TYPE = 5, -}; - u32 rtw_ch2freq(u32 ch); #endif /* _RTL8711_RF_H_ */ diff --git a/drivers/staging/r8188eu/include/usb_osintf.h b/drivers/staging/r8188eu/include/usb_osintf.h index 624298b4bd0b..3e777ca52745 100644 --- a/drivers/staging/r8188eu/include/usb_osintf.h +++ b/drivers/staging/r8188eu/include/usb_osintf.h @@ -16,7 +16,6 @@ extern int rtw_mc2u_disable; u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, enum bt_usb_request brequest, enum rt_usb_wvalue wvalue, u8 windex, void *data, u8 datalen, u8 isdirectionin); -int pm_netdev_open(struct net_device *pnetdev, u8 bnormal); void netdev_br_init(struct net_device *netdev); void dhcp_flag_bcast(struct adapter *priv, struct sk_buff *skb); void *scdb_findEntry(struct adapter *priv, unsigned char *ipAddr); diff --git a/drivers/staging/r8188eu/include/wifi.h b/drivers/staging/r8188eu/include/wifi.h index 193a557f0f47..0b0bd39a257f 100644 --- a/drivers/staging/r8188eu/include/wifi.h +++ b/drivers/staging/r8188eu/include/wifi.h @@ -13,32 +13,9 @@ #define BIT(x) (1 << (x)) #define WLAN_ETHHDR_LEN 14 -#define WLAN_ETHADDR_LEN 6 -#define WLAN_IEEE_OUI_LEN 3 -#define WLAN_ADDR_LEN 6 -#define WLAN_CRC_LEN 4 -#define WLAN_BSSID_LEN 6 -#define WLAN_BSS_TS_LEN 8 #define WLAN_HDR_A3_LEN 24 -#define WLAN_HDR_A4_LEN 30 #define WLAN_HDR_A3_QOS_LEN 26 -#define WLAN_HDR_A4_QOS_LEN 32 #define WLAN_SSID_MAXLEN 32 -#define WLAN_DATA_MAXLEN 2312 - -#define WLAN_A3_PN_OFFSET 24 -#define WLAN_A4_PN_OFFSET 30 - -#define WLAN_MIN_ETHFRM_LEN 60 -#define WLAN_MAX_ETHFRM_LEN 1514 -#define WLAN_ETHHDR_LEN 14 - -#define P80211CAPTURE_VERSION 0x80211001 - -/* This value is tested by WiFi 11n Test Plan 5.2.3. */ -/* This test verifies the WLAN NIC can update the NAV through sending - * the CTS with large duration. */ -#define WiFiNavUpperUs 30000 /* 30 ms */ enum WIFI_FRAME_TYPE { WIFI_MGT_TYPE = (0), @@ -487,13 +464,6 @@ static inline int IsFrameTypeCtrl(unsigned char *pframe) #define _STATUS_CODE_ 2 #define _TIMESTAMP_ 8 -#define AUTH_ODD_TO 0 -#define AUTH_EVEN_TO 1 - -#define WLAN_ETHCONV_ENCAP 1 -#define WLAN_ETHCONV_RFC1042 2 -#define WLAN_ETHCONV_8021h 3 - #define cap_ESS BIT(0) #define cap_IBSS BIT(1) #define cap_CFPollable BIT(2) @@ -632,13 +602,6 @@ enum ht_cap_ampdu_factor { #define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) #define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) -#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) -#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) -#define HT_INFO_STBC_PARAM_SECONDARY_BC ((u16) BIT(8)) -#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) -#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) -#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) - /* ===============WPS Section=============== */ /* For WPSv1.0 */ #define WPSOUI 0x0050f204 @@ -930,7 +893,7 @@ enum P2P_PROTO_WK_ID { P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, - P2P_AP_P2P_CH_SWITCH_PROCESS_WK =5, + P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5, P2P_RO_CH_WK = 6, }; @@ -949,26 +912,6 @@ enum P2P_PS_MODE { P2P_PS_MIX = 3, /* CTWindow and NoA */ }; -/* =====================WFD Section===================== */ -/* For Wi-Fi Display */ -#define WFD_ATTR_DEVICE_INFO 0x00 -#define WFD_ATTR_ASSOC_BSSID 0x01 -#define WFD_ATTR_COUPLED_SINK_INFO 0x06 -#define WFD_ATTR_LOCAL_IP_ADDR 0x08 -#define WFD_ATTR_SESSION_INFO 0x09 -#define WFD_ATTR_ALTER_MAC 0x0a - -/* For WFD Device Information Attribute */ -#define WFD_DEVINFO_SOURCE 0x0000 -#define WFD_DEVINFO_PSINK 0x0001 -#define WFD_DEVINFO_SSINK 0x0002 -#define WFD_DEVINFO_DUAL 0x0003 - -#define WFD_DEVINFO_SESSION_AVAIL 0x0010 -#define WFD_DEVINFO_WSD 0x0040 -#define WFD_DEVINFO_PC_TDLS 0x0080 -#define WFD_DEVINFO_HDCP_SUPPORT 0x0100 - #define IP_MCAST_MAC(mac) \ ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) #define ICMPV6_MCAST_MAC(mac) \ |