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path: root/drivers/thermal/mediatek/auxadc_thermal.c
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Diffstat (limited to 'drivers/thermal/mediatek/auxadc_thermal.c')
-rw-r--r--drivers/thermal/mediatek/auxadc_thermal.c111
1 files changed, 92 insertions, 19 deletions
diff --git a/drivers/thermal/mediatek/auxadc_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c
index ab730f9552d0..b6bb9eaafb74 100644
--- a/drivers/thermal/mediatek/auxadc_thermal.c
+++ b/drivers/thermal/mediatek/auxadc_thermal.c
@@ -31,6 +31,7 @@
#define AUXADC_CON2_V 0x010
#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
+#define APMIXED_SYS_TS_CON0 0x600
#define APMIXED_SYS_TS_CON1 0x604
/* Thermal Controller Registers */
@@ -281,6 +282,17 @@ enum mtk_thermal_version {
/* The calibration coefficient of sensor */
#define MT7986_CALIBRATION 165
+/* MT8365 */
+#define MT8365_TEMP_AUXADC_CHANNEL 11
+#define MT8365_CALIBRATION 164
+#define MT8365_NUM_CONTROLLER 1
+#define MT8365_NUM_BANKS 1
+#define MT8365_NUM_SENSORS 3
+#define MT8365_NUM_SENSORS_PER_ZONE 3
+#define MT8365_TS1 0
+#define MT8365_TS2 1
+#define MT8365_TS3 2
+
struct mtk_thermal;
struct thermal_bank_cfg {
@@ -307,6 +319,9 @@ struct mtk_thermal_data {
bool need_switch_bank;
struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
enum mtk_thermal_version version;
+ u32 apmixed_buffer_ctl_reg;
+ u32 apmixed_buffer_ctl_mask;
+ u32 apmixed_buffer_ctl_set;
};
struct mtk_thermal {
@@ -432,6 +447,24 @@ static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+/* MT8365 thermal sensor data */
+static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
+ MT8365_TS1, MT8365_TS2, MT8365_TS3
+};
+
+static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
+};
+
+static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
+};
+
+static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
+static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
+
+static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
+
/*
* The MT8173 thermal controller has four banks. Each bank can read up to
* four temperature sensors simultaneously. The MT8173 has a total of 5
@@ -507,6 +540,40 @@ static const struct mtk_thermal_data mt2701_thermal_data = {
};
/*
+ * The MT8365 thermal controller has one bank, which can read up to
+ * four temperature sensors simultaneously. The MT8365 has a total of 3
+ * temperature sensors.
+ *
+ * The thermal core only gets the maximum temperature of this one bank,
+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+ * Voltage Scaling) unit makes its decisions based on the same bank
+ * data.
+ */
+static const struct mtk_thermal_data mt8365_thermal_data = {
+ .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
+ .num_banks = MT8365_NUM_BANKS,
+ .num_sensors = MT8365_NUM_SENSORS,
+ .vts_index = mt8365_vts_index,
+ .cali_val = MT8365_CALIBRATION,
+ .num_controller = MT8365_NUM_CONTROLLER,
+ .controller_offset = mt8365_tc_offset,
+ .need_switch_bank = false,
+ .bank_data = {
+ {
+ .num_sensors = MT8365_NUM_SENSORS,
+ .sensors = mt8365_bank_data
+ },
+ },
+ .msr = mt8365_msr,
+ .adcpnp = mt8365_adcpnp,
+ .sensor_mux_values = mt8365_mux_values,
+ .version = MTK_THERMAL_V1,
+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
+ .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
+ .apmixed_buffer_ctl_set = 0,
+};
+
+/*
* The MT2712 thermal controller has one bank, which can read up to
* four temperature sensors simultaneously. The MT2712 has a total of 4
* temperature sensors.
@@ -560,6 +627,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = {
.adcpnp = mt7622_adcpnp,
.sensor_mux_values = mt7622_mux_values,
.version = MTK_THERMAL_V2,
+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
+ .apmixed_buffer_ctl_set = BIT(0),
};
/*
@@ -746,14 +816,6 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
mt, conf->bank_data[bank->id].sensors[i], raw);
- /*
- * The first read of a sensor often contains very high bogus
- * temperature value. Filter these out so that the system does
- * not immediately shut down.
- */
- if (temp > 200000)
- temp = 0;
-
if (temp > max)
max = temp;
}
@@ -763,7 +825,7 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
{
- struct mtk_thermal *mt = tz->devdata;
+ struct mtk_thermal *mt = thermal_zone_device_priv(tz);
int i;
int tempmax = INT_MIN;
@@ -1074,19 +1136,27 @@ static const struct of_device_id mtk_thermal_of_match[] = {
{
.compatible = "mediatek,mt8183-thermal",
.data = (void *)&mt8183_thermal_data,
+ },
+ {
+ .compatible = "mediatek,mt8365-thermal",
+ .data = (void *)&mt8365_thermal_data,
}, {
},
};
MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
+static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
+ void __iomem *apmixed_base)
{
- int tmp;
+ u32 tmp;
- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
- tmp &= ~(0x37);
- tmp |= 0x1;
- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
+ if (!mt->conf->apmixed_buffer_ctl_reg)
+ return;
+
+ tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
+ tmp &= mt->conf->apmixed_buffer_ctl_mask;
+ tmp |= mt->conf->apmixed_buffer_ctl_set;
+ writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
udelay(200);
}
@@ -1184,10 +1254,10 @@ static int mtk_thermal_probe(struct platform_device *pdev)
goto err_disable_clk_auxadc;
}
- if (mt->conf->version != MTK_THERMAL_V1) {
- mtk_thermal_turn_on_buffer(apmixed_base);
+ mtk_thermal_turn_on_buffer(mt, apmixed_base);
+
+ if (mt->conf->version != MTK_THERMAL_V2)
mtk_thermal_release_periodic_ts(mt, auxadc_base);
- }
if (mt->conf->version == MTK_THERMAL_V1)
mt->raw_to_mcelsius = raw_to_mcelsius_v1;
@@ -1203,6 +1273,9 @@ static int mtk_thermal_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, mt);
+ /* Delay for thermal banks to be ready */
+ msleep(30);
+
tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
&mtk_thermal_ops);
if (IS_ERR(tzdev)) {
@@ -1210,7 +1283,7 @@ static int mtk_thermal_probe(struct platform_device *pdev)
goto err_disable_clk_peri_therm;
}
- ret = devm_thermal_add_hwmon_sysfs(tzdev);
+ ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
if (ret)
dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");