diff options
Diffstat (limited to 'drivers/watchdog')
28 files changed, 592 insertions, 314 deletions
diff --git a/drivers/watchdog/asm9260_wdt.c b/drivers/watchdog/asm9260_wdt.c index 53da001f0838..7dd0da644a7f 100644 --- a/drivers/watchdog/asm9260_wdt.c +++ b/drivers/watchdog/asm9260_wdt.c @@ -82,7 +82,7 @@ static unsigned int asm9260_wdt_gettimeleft(struct watchdog_device *wdd) counter = ioread32(priv->iobase + HW_WDTV); - return DIV_ROUND_CLOSEST(counter, priv->wdt_freq); + return counter / priv->wdt_freq; } static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd) @@ -296,7 +296,7 @@ static int asm9260_wdt_probe(struct platform_device *pdev) if (ret) return ret; - priv->rst = devm_reset_control_get(&pdev->dev, "wdt_rst"); + priv->rst = devm_reset_control_get_exclusive(&pdev->dev, "wdt_rst"); if (IS_ERR(priv->rst)) return PTR_ERR(priv->rst); diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index 1c652582de40..79cc766cd30f 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -23,9 +23,21 @@ struct aspeed_wdt { u32 ctrl; }; +struct aspeed_wdt_config { + u32 ext_pulse_width_mask; +}; + +static const struct aspeed_wdt_config ast2400_config = { + .ext_pulse_width_mask = 0xff, +}; + +static const struct aspeed_wdt_config ast2500_config = { + .ext_pulse_width_mask = 0xfffff, +}; + static const struct of_device_id aspeed_wdt_of_table[] = { - { .compatible = "aspeed,ast2400-wdt" }, - { .compatible = "aspeed,ast2500-wdt" }, + { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config }, + { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config }, { }, }; MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); @@ -36,12 +48,45 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_CTRL 0x0C #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) #define WDT_CTRL_1MHZ_CLK BIT(4) #define WDT_CTRL_WDT_EXT BIT(3) #define WDT_CTRL_WDT_INTR BIT(2) #define WDT_CTRL_RESET_SYSTEM BIT(1) #define WDT_CTRL_ENABLE BIT(0) +/* + * WDT_RESET_WIDTH controls the characteristics of the external pulse (if + * enabled), specifically: + * + * * Pulse duration + * * Drive mode: push-pull vs open-drain + * * Polarity: Active high or active low + * + * Pulse duration configuration is available on both the AST2400 and AST2500, + * though the field changes between SoCs: + * + * AST2400: Bits 7:0 + * AST2500: Bits 19:0 + * + * This difference is captured in struct aspeed_wdt_config. + * + * The AST2500 exposes the drive mode and polarity options, but not in a + * regular fashion. For read purposes, bit 31 represents active high or low, + * and bit 30 represents push-pull or open-drain. With respect to write, magic + * values need to be written to the top byte to change the state of the drive + * mode and polarity bits. Any other value written to the top byte has no + * effect on the state of the drive mode or polarity bits. However, the pulse + * width value must be preserved (as desired) if written. + */ +#define WDT_RESET_WIDTH 0x18 +#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) +#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) +#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) +#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) +#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) +#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) + #define WDT_RESTART_MAGIC 0x4755 /* 32 bits at 1MHz, in milliseconds */ @@ -138,8 +183,13 @@ static const struct watchdog_info aspeed_wdt_info = { static int aspeed_wdt_probe(struct platform_device *pdev) { + const struct aspeed_wdt_config *config; + const struct of_device_id *ofdid; struct aspeed_wdt *wdt; struct resource *res; + struct device_node *np; + const char *reset_type; + u32 duration; int ret; wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); @@ -164,20 +214,88 @@ static int aspeed_wdt_probe(struct platform_device *pdev) wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); + np = pdev->dev.of_node; + + ofdid = of_match_node(aspeed_wdt_of_table, np); + if (!ofdid) + return -EINVAL; + config = ofdid->data; + + wdt->ctrl = WDT_CTRL_1MHZ_CLK; + /* * Control reset on a per-device basis to ensure the - * host is not affected by a BMC reboot, so only reset - * the SOC and not the full chip + * host is not affected by a BMC reboot */ - wdt->ctrl = WDT_CTRL_RESET_MODE_SOC | - WDT_CTRL_1MHZ_CLK | - WDT_CTRL_RESET_SYSTEM; + ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); + if (ret) { + wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; + } else { + if (!strcmp(reset_type, "cpu")) + wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU; + else if (!strcmp(reset_type, "soc")) + wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC; + else if (!strcmp(reset_type, "system")) + wdt->ctrl |= WDT_CTRL_RESET_SYSTEM; + else if (strcmp(reset_type, "none")) + return -EINVAL; + } + if (of_property_read_bool(np, "aspeed,external-signal")) + wdt->ctrl |= WDT_CTRL_WDT_EXT; + + writel(wdt->ctrl, wdt->base + WDT_CTRL); if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { aspeed_wdt_start(&wdt->wdd); set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); } + if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) { + u32 reg = readl(wdt->base + WDT_RESET_WIDTH); + + reg &= config->ext_pulse_width_mask; + if (of_property_read_bool(np, "aspeed,ext-push-pull")) + reg |= WDT_PUSH_PULL_MAGIC; + else + reg |= WDT_OPEN_DRAIN_MAGIC; + + writel(reg, wdt->base + WDT_RESET_WIDTH); + + reg &= config->ext_pulse_width_mask; + if (of_property_read_bool(np, "aspeed,ext-active-high")) + reg |= WDT_ACTIVE_HIGH_MAGIC; + else + reg |= WDT_ACTIVE_LOW_MAGIC; + + writel(reg, wdt->base + WDT_RESET_WIDTH); + } + + if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { + u32 max_duration = config->ext_pulse_width_mask + 1; + + if (duration == 0 || duration > max_duration) { + dev_err(&pdev->dev, "Invalid pulse duration: %uus\n", + duration); + duration = max(1U, min(max_duration, duration)); + dev_info(&pdev->dev, "Pulse duration set to %uus\n", + duration); + } + + /* + * The watchdog is always configured with a 1MHz source, so + * there is no need to scale the microsecond value. However we + * need to offset it - from the datasheet: + * + * "This register decides the asserting duration of wdt_ext and + * wdt_rstarm signal. The default value is 0xFF. It means the + * default asserting duration of wdt_ext and wdt_rstarm is + * 256us." + * + * This implies a value of 0 gives a 1us pulse. + */ + writel(duration - 1, wdt->base + WDT_RESET_WIDTH); + } + ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd); if (ret) { dev_err(&pdev->dev, "failed to register\n"); diff --git a/drivers/watchdog/bcm7038_wdt.c b/drivers/watchdog/bcm7038_wdt.c index c1b8e534fb55..f88f546e8050 100644 --- a/drivers/watchdog/bcm7038_wdt.c +++ b/drivers/watchdog/bcm7038_wdt.c @@ -136,7 +136,9 @@ static int bcm7038_wdt_probe(struct platform_device *pdev) wdt->clk = devm_clk_get(dev, NULL); /* If unable to get clock, use default frequency */ if (!IS_ERR(wdt->clk)) { - clk_prepare_enable(wdt->clk); + err = clk_prepare_enable(wdt->clk); + if (err) + return err; wdt->rate = clk_get_rate(wdt->clk); /* Prevent divide-by-zero exception */ if (!wdt->rate) diff --git a/drivers/watchdog/cadence_wdt.c b/drivers/watchdog/cadence_wdt.c index 05c000081e9d..064cf7b6c1c5 100644 --- a/drivers/watchdog/cadence_wdt.c +++ b/drivers/watchdog/cadence_wdt.c @@ -52,12 +52,12 @@ static int wdt_timeout; static int nowayout = WATCHDOG_NOWAYOUT; -module_param(wdt_timeout, int, 0); +module_param(wdt_timeout, int, 0644); MODULE_PARM_DESC(wdt_timeout, "Watchdog time in seconds. (default=" __MODULE_STRING(CDNS_WDT_DEFAULT_TIMEOUT) ")"); -module_param(nowayout, int, 0); +module_param(nowayout, int, 0644); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); @@ -368,7 +368,7 @@ static int cdns_wdt_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, wdt); - dev_dbg(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds%s\n", + dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds%s\n", wdt->regs, cdns_wdt_device->timeout, nowayout ? ", nowayout" : ""); diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index 38dd60f0cfcc..4410337f4f7f 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c @@ -218,7 +218,7 @@ static const struct watchdog_info coh901327_ident = { .identity = DRV_NAME, }; -static struct watchdog_ops coh901327_ops = { +static const struct watchdog_ops coh901327_ops = { .owner = THIS_MODULE, .start = coh901327_start, .stop = coh901327_stop, diff --git a/drivers/watchdog/da9063_wdt.c b/drivers/watchdog/da9063_wdt.c index 4691c5509129..2a20fc163ed0 100644 --- a/drivers/watchdog/da9063_wdt.c +++ b/drivers/watchdog/da9063_wdt.c @@ -36,11 +36,6 @@ static const unsigned int wdt_timeout[] = { 0, 2, 4, 8, 16, 32, 65, 131 }; #define DA9063_WDG_TIMEOUT wdt_timeout[3] #define DA9063_RESET_PROTECTION_MS 256 -struct da9063_watchdog { - struct da9063 *da9063; - struct watchdog_device wdtdev; -}; - static unsigned int da9063_wdt_timeout_to_sel(unsigned int secs) { unsigned int i; @@ -61,14 +56,14 @@ static int _da9063_wdt_set_timeout(struct da9063 *da9063, unsigned int regval) static int da9063_wdt_start(struct watchdog_device *wdd) { - struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd); + struct da9063 *da9063 = watchdog_get_drvdata(wdd); unsigned int selector; int ret; - selector = da9063_wdt_timeout_to_sel(wdt->wdtdev.timeout); - ret = _da9063_wdt_set_timeout(wdt->da9063, selector); + selector = da9063_wdt_timeout_to_sel(wdd->timeout); + ret = _da9063_wdt_set_timeout(da9063, selector); if (ret) - dev_err(wdt->da9063->dev, "Watchdog failed to start (err = %d)\n", + dev_err(da9063->dev, "Watchdog failed to start (err = %d)\n", ret); return ret; @@ -76,13 +71,13 @@ static int da9063_wdt_start(struct watchdog_device *wdd) static int da9063_wdt_stop(struct watchdog_device *wdd) { - struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd); + struct da9063 *da9063 = watchdog_get_drvdata(wdd); int ret; - ret = regmap_update_bits(wdt->da9063->regmap, DA9063_REG_CONTROL_D, + ret = regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_D, DA9063_TWDSCALE_MASK, DA9063_TWDSCALE_DISABLE); if (ret) - dev_alert(wdt->da9063->dev, "Watchdog failed to stop (err = %d)\n", + dev_alert(da9063->dev, "Watchdog failed to stop (err = %d)\n", ret); return ret; @@ -90,13 +85,13 @@ static int da9063_wdt_stop(struct watchdog_device *wdd) static int da9063_wdt_ping(struct watchdog_device *wdd) { - struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd); + struct da9063 *da9063 = watchdog_get_drvdata(wdd); int ret; - ret = regmap_write(wdt->da9063->regmap, DA9063_REG_CONTROL_F, + ret = regmap_write(da9063->regmap, DA9063_REG_CONTROL_F, DA9063_WATCHDOG); if (ret) - dev_alert(wdt->da9063->dev, "Failed to ping the watchdog (err = %d)\n", + dev_alert(da9063->dev, "Failed to ping the watchdog (err = %d)\n", ret); return ret; @@ -105,14 +100,14 @@ static int da9063_wdt_ping(struct watchdog_device *wdd) static int da9063_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout) { - struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd); + struct da9063 *da9063 = watchdog_get_drvdata(wdd); unsigned int selector; int ret; selector = da9063_wdt_timeout_to_sel(timeout); - ret = _da9063_wdt_set_timeout(wdt->da9063, selector); + ret = _da9063_wdt_set_timeout(da9063, selector); if (ret) - dev_err(wdt->da9063->dev, "Failed to set watchdog timeout (err = %d)\n", + dev_err(da9063->dev, "Failed to set watchdog timeout (err = %d)\n", ret); else wdd->timeout = wdt_timeout[selector]; @@ -123,13 +118,13 @@ static int da9063_wdt_set_timeout(struct watchdog_device *wdd, static int da9063_wdt_restart(struct watchdog_device *wdd, unsigned long action, void *data) { - struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd); + struct da9063 *da9063 = watchdog_get_drvdata(wdd); int ret; - ret = regmap_write(wdt->da9063->regmap, DA9063_REG_CONTROL_F, + ret = regmap_write(da9063->regmap, DA9063_REG_CONTROL_F, DA9063_SHUTDOWN); if (ret) - dev_alert(wdt->da9063->dev, "Failed to shutdown (err = %d)\n", + dev_alert(da9063->dev, "Failed to shutdown (err = %d)\n", ret); return ret; @@ -152,7 +147,7 @@ static const struct watchdog_ops da9063_watchdog_ops = { static int da9063_wdt_probe(struct platform_device *pdev) { struct da9063 *da9063; - struct da9063_watchdog *wdt; + struct watchdog_device *wdd; if (!pdev->dev.parent) return -EINVAL; @@ -161,27 +156,25 @@ static int da9063_wdt_probe(struct platform_device *pdev) if (!da9063) return -EINVAL; - wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); - if (!wdt) + wdd = devm_kzalloc(&pdev->dev, sizeof(*wdd), GFP_KERNEL); + if (!wdd) return -ENOMEM; - wdt->da9063 = da9063; - - wdt->wdtdev.info = &da9063_watchdog_info; - wdt->wdtdev.ops = &da9063_watchdog_ops; - wdt->wdtdev.min_timeout = DA9063_WDT_MIN_TIMEOUT; - wdt->wdtdev.max_timeout = DA9063_WDT_MAX_TIMEOUT; - wdt->wdtdev.min_hw_heartbeat_ms = DA9063_RESET_PROTECTION_MS; - wdt->wdtdev.timeout = DA9063_WDG_TIMEOUT; - wdt->wdtdev.parent = &pdev->dev; + wdd->info = &da9063_watchdog_info; + wdd->ops = &da9063_watchdog_ops; + wdd->min_timeout = DA9063_WDT_MIN_TIMEOUT; + wdd->max_timeout = DA9063_WDT_MAX_TIMEOUT; + wdd->min_hw_heartbeat_ms = DA9063_RESET_PROTECTION_MS; + wdd->timeout = DA9063_WDG_TIMEOUT; + wdd->parent = &pdev->dev; - wdt->wdtdev.status = WATCHDOG_NOWAYOUT_INIT_STATUS; + wdd->status = WATCHDOG_NOWAYOUT_INIT_STATUS; - watchdog_set_restart_priority(&wdt->wdtdev, 128); + watchdog_set_restart_priority(wdd, 128); - watchdog_set_drvdata(&wdt->wdtdev, wdt); + watchdog_set_drvdata(wdd, da9063); - return devm_watchdog_register_device(&pdev->dev, &wdt->wdtdev); + return devm_watchdog_register_device(&pdev->dev, wdd); } static struct platform_driver da9063_wdt_driver = { diff --git a/drivers/watchdog/diag288_wdt.c b/drivers/watchdog/diag288_wdt.c index 6f591084bb7a..806a04a676b7 100644 --- a/drivers/watchdog/diag288_wdt.c +++ b/drivers/watchdog/diag288_wdt.c @@ -213,7 +213,7 @@ static const struct watchdog_ops wdt_ops = { .set_timeout = wdt_set_timeout, }; -static struct watchdog_info wdt_info = { +static const struct watchdog_info wdt_info = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 0, .identity = "z Watchdog", diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index c4f65873bfa4..347f0389b089 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -306,15 +306,16 @@ static int iTCO_wdt_ping(struct watchdog_device *wd_dev) iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout); - /* Reset the timeout status bit so that the timer - * needs to count down twice again before rebooting */ - outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */ - /* Reload the timer by writing to the TCO Timer Counter register */ - if (p->iTCO_version >= 2) + if (p->iTCO_version >= 2) { outw(0x01, TCO_RLD(p)); - else if (p->iTCO_version == 1) + } else if (p->iTCO_version == 1) { + /* Reset the timeout status bit so that the timer + * needs to count down twice again before rebooting */ + outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */ + outb(0x01, TCO_RLD(p)); + } spin_unlock(&p->io_lock); return 0; @@ -327,8 +328,11 @@ static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) unsigned char val8; unsigned int tmrval; - /* The timer counts down twice before rebooting */ - tmrval = seconds_to_ticks(p, t) / 2; + tmrval = seconds_to_ticks(p, t); + + /* For TCO v1 the timer counts down twice before rebooting */ + if (p->iTCO_version == 1) + tmrval /= 2; /* from the specs: */ /* "Values of 0h-3h are ignored and should not be attempted" */ @@ -381,8 +385,6 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) spin_lock(&p->io_lock); val16 = inw(TCO_RLD(p)); val16 &= 0x3ff; - if (!(inw(TCO1_STS(p)) & 0x0008)) - val16 += (inw(TCOv2_TMR(p)) & 0x3ff); spin_unlock(&p->io_lock); time_left = ticks_to_seconds(p, val16); diff --git a/drivers/watchdog/it87_wdt.c b/drivers/watchdog/it87_wdt.c index dd1e7eaef50f..e96faea24925 100644 --- a/drivers/watchdog/it87_wdt.c +++ b/drivers/watchdog/it87_wdt.c @@ -253,7 +253,7 @@ static const struct watchdog_info ident = { .identity = WATCHDOG_NAME, }; -static struct watchdog_ops wdt_ops = { +static const struct watchdog_ops wdt_ops = { .owner = THIS_MODULE, .start = wdt_start, .stop = wdt_stop, diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index e0823677d8c1..7f43cefa0eae 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -4,6 +4,7 @@ * by the Free Software Foundation. * * Copyright (C) 2010 John Crispin <john@phrozen.org> + * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de> * Based on EP93xx wdt driver */ @@ -17,9 +18,20 @@ #include <linux/uaccess.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> #include <lantiq_soc.h> +#define LTQ_XRX_RCU_RST_STAT 0x0014 +#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31) + +/* CPU0 Reset Source Register */ +#define LTQ_FALCON_SYS1_CPU0RS 0x0060 +/* reset cause mask */ +#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007 +#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02 + /* * Section 3.4 of the datasheet * The password sequence protects the WDT control register from unintended @@ -186,16 +198,70 @@ static struct miscdevice ltq_wdt_miscdev = { .fops = <q_wdt_fops, }; +typedef int (*ltq_wdt_bootstatus_set)(struct platform_device *pdev); + +static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *rcu_regmap; + u32 val; + int err; + + rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap"); + if (IS_ERR(rcu_regmap)) + return PTR_ERR(rcu_regmap); + + err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val); + if (err) + return err; + + if (val & LTQ_XRX_RCU_RST_STAT_WDT) + ltq_wdt_bootstatus = WDIOF_CARDRESET; + + return 0; +} + +static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *rcu_regmap; + u32 val; + int err; + + rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "lantiq,rcu"); + if (IS_ERR(rcu_regmap)) + return PTR_ERR(rcu_regmap); + + err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val); + if (err) + return err; + + if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT) + ltq_wdt_bootstatus = WDIOF_CARDRESET; + + return 0; +} + static int ltq_wdt_probe(struct platform_device *pdev) { struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); struct clk *clk; + ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set; + int ret; ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(ltq_wdt_membase)) return PTR_ERR(ltq_wdt_membase); + ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev); + if (ltq_wdt_bootstatus_set) { + ret = ltq_wdt_bootstatus_set(pdev); + if (ret) + return ret; + } + /* we do not need to enable the clock as it is always running */ clk = clk_get_io(); if (IS_ERR(clk)) { @@ -205,10 +271,6 @@ ltq_wdt_probe(struct platform_device *pdev) ltq_io_region_clk_rate = clk_get_rate(clk); clk_put(clk); - /* find out if the watchdog caused the last reboot */ - if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST) - ltq_wdt_bootstatus = WDIOF_CARDRESET; - dev_info(&pdev->dev, "Init done\n"); return misc_register(<q_wdt_miscdev); } @@ -222,7 +284,9 @@ ltq_wdt_remove(struct platform_device *pdev) } static const struct of_device_id ltq_wdt_match[] = { - { .compatible = "lantiq,wdt" }, + { .compatible = "lantiq,wdt", .data = NULL}, + { .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx }, + { .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon }, {}, }; MODULE_DEVICE_TABLE(of, ltq_wdt_match); diff --git a/drivers/watchdog/max77620_wdt.c b/drivers/watchdog/max77620_wdt.c index 68c41fa2be27..2c9f53eaff4f 100644 --- a/drivers/watchdog/max77620_wdt.c +++ b/drivers/watchdog/max77620_wdt.c @@ -201,7 +201,7 @@ static int max77620_wdt_remove(struct platform_device *pdev) return 0; } -static struct platform_device_id max77620_wdt_devtype[] = { +static const struct platform_device_id max77620_wdt_devtype[] = { { .name = "max77620-watchdog", }, { }, }; diff --git a/drivers/watchdog/mei_wdt.c b/drivers/watchdog/mei_wdt.c index b29c6fde7473..ea60b29494fb 100644 --- a/drivers/watchdog/mei_wdt.c +++ b/drivers/watchdog/mei_wdt.c @@ -670,7 +670,7 @@ static int mei_wdt_remove(struct mei_cl_device *cldev) #define MEI_UUID_WD UUID_LE(0x05B79A6F, 0x4628, 0x4D7F, \ 0x89, 0x9D, 0xA9, 0x15, 0x14, 0xCB, 0x32, 0xAB) -static struct mei_cl_device_id mei_wdt_tbl[] = { +static const struct mei_cl_device_id mei_wdt_tbl[] = { { .uuid = MEI_UUID_WD, .version = MEI_CL_VERSION_ANY }, /* required last entry */ { } diff --git a/drivers/watchdog/meson_wdt.c b/drivers/watchdog/meson_wdt.c index 491b9bf13d84..304274c67735 100644 --- a/drivers/watchdog/meson_wdt.c +++ b/drivers/watchdog/meson_wdt.c @@ -155,7 +155,9 @@ static const struct watchdog_ops meson_wdt_ops = { static const struct of_device_id meson_wdt_dt_ids[] = { { .compatible = "amlogic,meson6-wdt", .data = &meson6_wdt_data }, + { .compatible = "amlogic,meson8-wdt", .data = &meson6_wdt_data }, { .compatible = "amlogic,meson8b-wdt", .data = &meson8b_wdt_data }, + { .compatible = "amlogic,meson8m2-wdt", .data = &meson8b_wdt_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_wdt_dt_ids); diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 48a06067075d..db38f8017218 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -105,7 +105,7 @@ static int mt7621_wdt_bootcause(void) return 0; } -static struct watchdog_info mt7621_wdt_info = { +static const struct watchdog_info mt7621_wdt_info = { .identity = "Mediatek Watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, }; @@ -135,7 +135,7 @@ static int mt7621_wdt_probe(struct platform_device *pdev) if (IS_ERR(mt7621_wdt_base)) return PTR_ERR(mt7621_wdt_base); - mt7621_wdt_reset = devm_reset_control_get(&pdev->dev, NULL); + mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (!IS_ERR(mt7621_wdt_reset)) reset_control_deassert(mt7621_wdt_reset); diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c index b5cdceb36cff..0ec419a3f7ed 100644 --- a/drivers/watchdog/octeon-wdt-main.c +++ b/drivers/watchdog/octeon-wdt-main.c @@ -1,7 +1,7 @@ /* * Octeon Watchdog driver * - * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks + * Copyright (C) 2007-2017 Cavium, Inc. * * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. * @@ -59,20 +59,23 @@ #include <linux/interrupt.h> #include <linux/watchdog.h> #include <linux/cpumask.h> -#include <linux/bitops.h> -#include <linux/kernel.h> #include <linux/module.h> -#include <linux/string.h> #include <linux/delay.h> #include <linux/cpu.h> -#include <linux/smp.h> -#include <linux/fs.h> #include <linux/irq.h> #include <asm/mipsregs.h> #include <asm/uasm.h> #include <asm/octeon/octeon.h> +#include <asm/octeon/cvmx-boot-vector.h> +#include <asm/octeon/cvmx-ciu2-defs.h> +#include <asm/octeon/cvmx-rst-defs.h> + +/* Watchdog interrupt major block number (8 MSBs of intsn) */ +#define WD_BLOCK_NUMBER 0x01 + +static int divisor; /* The count needed to achieve timeout_sec. */ static unsigned int timeout_cnt; @@ -84,7 +87,7 @@ static unsigned int max_timeout_sec; static unsigned int timeout_sec; /* Set to non-zero when userspace countdown mode active */ -static int do_coundown; +static bool do_countdown; static unsigned int countdown_reset; static unsigned int per_cpu_countdown[NR_CPUS]; @@ -92,152 +95,38 @@ static cpumask_t irq_enabled_cpus; #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ +#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) + static int heartbeat = WD_TIMO; -module_param(heartbeat, int, S_IRUGO); +module_param(heartbeat, int, 0444); MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0 < heartbeat, default=" __MODULE_STRING(WD_TIMO) ")"); static bool nowayout = WATCHDOG_NOWAYOUT; -module_param(nowayout, bool, S_IRUGO); +module_param(nowayout, bool, 0444); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -static u32 nmi_stage1_insns[64] __initdata; -/* We need one branch and therefore one relocation per target label. */ -static struct uasm_label labels[5] __initdata; -static struct uasm_reloc relocs[5] __initdata; - -enum lable_id { - label_enter_bootloader = 1 -}; +static int disable; +module_param(disable, int, 0444); +MODULE_PARM_DESC(disable, + "Disable the watchdog entirely (default=0)"); -/* Some CP0 registers */ -#define K0 26 -#define C0_CVMMEMCTL 11, 7 -#define C0_STATUS 12, 0 -#define C0_EBASE 15, 1 -#define C0_DESAVE 31, 0 +static struct cvmx_boot_vector_element *octeon_wdt_bootvector; void octeon_wdt_nmi_stage2(void); -static void __init octeon_wdt_build_stage1(void) -{ - int i; - int len; - u32 *p = nmi_stage1_insns; -#ifdef CONFIG_HOTPLUG_CPU - struct uasm_label *l = labels; - struct uasm_reloc *r = relocs; -#endif - - /* - * For the next few instructions running the debugger may - * cause corruption of k0 in the saved registers. Since we're - * about to crash, nobody probably cares. - * - * Save K0 into the debug scratch register - */ - uasm_i_dmtc0(&p, K0, C0_DESAVE); - - uasm_i_mfc0(&p, K0, C0_STATUS); -#ifdef CONFIG_HOTPLUG_CPU - if (octeon_bootloader_entry_addr) - uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), - label_enter_bootloader); -#endif - /* Force 64-bit addressing enabled */ - uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX); - uasm_i_mtc0(&p, K0, C0_STATUS); - -#ifdef CONFIG_HOTPLUG_CPU - if (octeon_bootloader_entry_addr) { - uasm_i_mfc0(&p, K0, C0_EBASE); - /* Coreid number in K0 */ - uasm_i_andi(&p, K0, K0, 0xf); - /* 8 * coreid in bits 16-31 */ - uasm_i_dsll_safe(&p, K0, K0, 3 + 16); - uasm_i_ori(&p, K0, K0, 0x8001); - uasm_i_dsll_safe(&p, K0, K0, 16); - uasm_i_ori(&p, K0, K0, 0x0700); - uasm_i_drotr_safe(&p, K0, K0, 32); - /* - * Should result in: 0x8001,0700,0000,8*coreid which is - * CVMX_CIU_WDOGX(coreid) - 0x0500 - * - * Now ld K0, CVMX_CIU_WDOGX(coreid) - */ - uasm_i_ld(&p, K0, 0x500, K0); - /* - * If bit one set handle the NMI as a watchdog event. - * otherwise transfer control to bootloader. - */ - uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader); - uasm_i_nop(&p); - } -#endif - - /* Clear Dcache so cvmseg works right. */ - uasm_i_cache(&p, 1, 0, 0); - - /* Use K0 to do a read/modify/write of CVMMEMCTL */ - uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL); - /* Clear out the size of CVMSEG */ - uasm_i_dins(&p, K0, 0, 0, 6); - /* Set CVMSEG to its largest value */ - uasm_i_ori(&p, K0, K0, 0x1c0 | 54); - /* Store the CVMMEMCTL value */ - uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL); - - /* Load the address of the second stage handler */ - UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2); - uasm_i_jr(&p, K0); - uasm_i_dmfc0(&p, K0, C0_DESAVE); - -#ifdef CONFIG_HOTPLUG_CPU - if (octeon_bootloader_entry_addr) { - uasm_build_label(&l, p, label_enter_bootloader); - /* Jump to the bootloader and restore K0 */ - UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr); - uasm_i_jr(&p, K0); - uasm_i_dmfc0(&p, K0, C0_DESAVE); - } -#endif - uasm_resolve_relocs(relocs, labels); - - len = (int)(p - nmi_stage1_insns); - pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len); - - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < len; i++) - pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]); - pr_debug("\t.set pop\n"); - - if (len > 32) - panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", - len); -} - static int cpu2core(int cpu) { #ifdef CONFIG_SMP - return cpu_logical_map(cpu); + return cpu_logical_map(cpu) & 0x3f; #else return cvmx_get_core_num(); #endif } -static int core2cpu(int coreid) -{ -#ifdef CONFIG_SMP - return cpu_number_map(coreid); -#else - return 0; -#endif -} - /** * Poke the watchdog when an interrupt is received * @@ -248,13 +137,14 @@ static int core2cpu(int coreid) */ static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) { - unsigned int core = cvmx_get_core_num(); - int cpu = core2cpu(core); + int cpu = raw_smp_processor_id(); + unsigned int core = cpu2core(cpu); + int node = cpu_to_node(cpu); - if (do_coundown) { + if (do_countdown) { if (per_cpu_countdown[cpu] > 0) { /* We're alive, poke the watchdog */ - cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); per_cpu_countdown[cpu]--; } else { /* Bad news, you are about to reboot. */ @@ -263,7 +153,7 @@ static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) } } else { /* Not open, just ping away... */ - cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); } return IRQ_HANDLED; } @@ -338,10 +228,10 @@ void octeon_wdt_nmi_stage3(u64 reg[32]) u64 cp0_epc = read_c0_epc(); /* Delay so output from all cores output is not jumbled together. */ - __delay(100000000ull * coreid); + udelay(85000 * coreid); octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); - octeon_wdt_write_hex(coreid, 1); + octeon_wdt_write_hex(coreid, 2); octeon_wdt_write_string(" ***\r\n"); for (i = 0; i < 32; i++) { octeon_wdt_write_string("\t"); @@ -364,33 +254,98 @@ void octeon_wdt_nmi_stage3(u64 reg[32]) octeon_wdt_write_hex(cp0_cause, 16); octeon_wdt_write_string("\r\n"); - octeon_wdt_write_string("\tsum0\t0x"); - octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); - octeon_wdt_write_string("\ten0\t0x"); - octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); - octeon_wdt_write_string("\r\n"); + /* The CIU register is different for each Octeon model. */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { + octeon_wdt_write_string("\tsrc_wd\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); + octeon_wdt_write_string("\ten_wd\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); + octeon_wdt_write_string("\r\n"); + octeon_wdt_write_string("\tsrc_rml\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); + octeon_wdt_write_string("\ten_rml\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); + octeon_wdt_write_string("\r\n"); + octeon_wdt_write_string("\tsum\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); + octeon_wdt_write_string("\r\n"); + } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { + octeon_wdt_write_string("\tsum0\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); + octeon_wdt_write_string("\ten0\t0x"); + octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); + octeon_wdt_write_string("\r\n"); + } octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); + + /* + * G-30204: We must trigger a soft reset before watchdog + * does an incomplete job of doing it. + */ + if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { + u64 scr; + unsigned int node = cvmx_get_node_num(); + unsigned int lcore = cvmx_get_local_core_num(); + union cvmx_ciu_wdogx ciu_wdog; + + /* + * Wait for other cores to print out information, but + * not too long. Do the soft reset before watchdog + * can trigger it. + */ + do { + ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); + } while (ciu_wdog.s.cnt > 0x10000); + + scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); + scr |= 1 << 11; /* Indicate watchdog in bit 11 */ + cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); + cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); + } +} + +static int octeon_wdt_cpu_to_irq(int cpu) +{ + unsigned int coreid; + int node; + int irq; + + coreid = cpu2core(cpu); + node = cpu_to_node(cpu); + + if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { + struct irq_domain *domain; + int hwirq; + + domain = octeon_irq_get_block_domain(node, + WD_BLOCK_NUMBER); + hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; + irq = irq_find_mapping(domain, hwirq); + } else { + irq = OCTEON_IRQ_WDOG0 + coreid; + } + return irq; } static int octeon_wdt_cpu_pre_down(unsigned int cpu) { unsigned int core; - unsigned int irq; + int node; union cvmx_ciu_wdogx ciu_wdog; core = cpu2core(cpu); - irq = OCTEON_IRQ_WDOG0 + core; + node = cpu_to_node(cpu); /* Poke the watchdog to clear out its state */ - cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); /* Disable the hardware. */ ciu_wdog.u64 = 0; - cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); + cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); - free_irq(irq, octeon_wdt_poke_irq); + free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); return 0; } @@ -399,31 +354,56 @@ static int octeon_wdt_cpu_online(unsigned int cpu) unsigned int core; unsigned int irq; union cvmx_ciu_wdogx ciu_wdog; + int node; + struct irq_domain *domain; + int hwirq; core = cpu2core(cpu); + node = cpu_to_node(cpu); + + octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; /* Disable it before doing anything with the interrupts. */ ciu_wdog.u64 = 0; - cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); + cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); per_cpu_countdown[cpu] = countdown_reset; - irq = OCTEON_IRQ_WDOG0 + core; + if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { + /* Must get the domain for the watchdog block */ + domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); + + /* Get a irq for the wd intsn (hardware interrupt) */ + hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; + irq = irq_create_mapping(domain, hwirq); + irqd_set_trigger_type(irq_get_irq_data(irq), + IRQ_TYPE_EDGE_RISING); + } else + irq = OCTEON_IRQ_WDOG0 + core; if (request_irq(irq, octeon_wdt_poke_irq, IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) panic("octeon_wdt: Couldn't obtain irq %d", irq); + /* Must set the irq affinity here */ + if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { + cpumask_t mask; + + cpumask_clear(&mask); + cpumask_set_cpu(cpu, &mask); + irq_set_affinity(irq, &mask); + } + cpumask_set_cpu(cpu, &irq_enabled_cpus); /* Poke the watchdog to clear out its state */ - cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); /* Finally enable the watchdog now that all handlers are installed */ ciu_wdog.u64 = 0; ciu_wdog.s.len = timeout_cnt; ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ - cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); + cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); return 0; } @@ -432,17 +412,20 @@ static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) { int cpu; int coreid; + int node; + + if (disable) + return 0; for_each_online_cpu(cpu) { coreid = cpu2core(cpu); - cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); + node = cpu_to_node(cpu); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); per_cpu_countdown[cpu] = countdown_reset; - if ((countdown_reset || !do_coundown) && + if ((countdown_reset || !do_countdown) && !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { /* We have to enable the irq */ - int irq = OCTEON_IRQ_WDOG0 + coreid; - - enable_irq(irq); + enable_irq(octeon_wdt_cpu_to_irq(cpu)); cpumask_set_cpu(cpu, &irq_enabled_cpus); } } @@ -472,7 +455,7 @@ static void octeon_wdt_calc_parameters(int t) countdown_reset = periods > 2 ? periods - 2 : 0; heartbeat = t; - timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8; + timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; } static int octeon_wdt_set_timeout(struct watchdog_device *wdog, @@ -481,20 +464,25 @@ static int octeon_wdt_set_timeout(struct watchdog_device *wdog, int cpu; int coreid; union cvmx_ciu_wdogx ciu_wdog; + int node; if (t <= 0) return -1; octeon_wdt_calc_parameters(t); + if (disable) + return 0; + for_each_online_cpu(cpu) { coreid = cpu2core(cpu); - cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); + node = cpu_to_node(cpu); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); ciu_wdog.u64 = 0; ciu_wdog.s.len = timeout_cnt; ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ - cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); - cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); + cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); + cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); } octeon_wdt_ping(wdog); /* Get the irqs back on. */ return 0; @@ -503,13 +491,13 @@ static int octeon_wdt_set_timeout(struct watchdog_device *wdog, static int octeon_wdt_start(struct watchdog_device *wdog) { octeon_wdt_ping(wdog); - do_coundown = 1; + do_countdown = 1; return 0; } static int octeon_wdt_stop(struct watchdog_device *wdog) { - do_coundown = 0; + do_countdown = 0; octeon_wdt_ping(wdog); return 0; } @@ -540,14 +528,25 @@ static enum cpuhp_state octeon_wdt_online; */ static int __init octeon_wdt_init(void) { - int i; int ret; - u64 *ptr; + + octeon_wdt_bootvector = cvmx_boot_vector_get(); + if (!octeon_wdt_bootvector) { + pr_err("Error: Cannot allocate boot vector.\n"); + return -ENOMEM; + } + + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + divisor = 0x200; + else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) + divisor = 0x400; + else + divisor = 0x100; /* * Watchdog time expiration length = The 16 bits of LEN * represent the most significant bits of a 24 bit decrementer - * that decrements every 256 cycles. + * that decrements every divisor cycle. * * Try for a timeout of 5 sec, if that fails a smaller number * of even seconds, @@ -555,8 +554,7 @@ static int __init octeon_wdt_init(void) max_timeout_sec = 6; do { max_timeout_sec--; - timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * - max_timeout_sec) >> 8; + timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; } while (timeout_cnt > 65535); BUG_ON(timeout_cnt == 0); @@ -576,16 +574,10 @@ static int __init octeon_wdt_init(void) return ret; } - /* Build the NMI handler ... */ - octeon_wdt_build_stage1(); - - /* ... and install it. */ - ptr = (u64 *) nmi_stage1_insns; - for (i = 0; i < 16; i++) { - cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); - cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]); + if (disable) { + pr_notice("disabled\n"); + return 0; } - cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); cpumask_clear(&irq_enabled_cpus); @@ -607,6 +599,10 @@ err: static void __exit octeon_wdt_cleanup(void) { watchdog_unregister_device(&octeon_wdt); + + if (disable) + return; + cpuhp_remove_state(octeon_wdt_online); /* @@ -617,7 +613,7 @@ static void __exit octeon_wdt_cleanup(void) } MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); -MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver."); +MODULE_AUTHOR("Cavium Inc. <support@cavium.com>"); +MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); module_init(octeon_wdt_init); module_exit(octeon_wdt_cleanup); diff --git a/drivers/watchdog/octeon-wdt-nmi.S b/drivers/watchdog/octeon-wdt-nmi.S index 8a900a5e3233..97f6eb7b5a8e 100644 --- a/drivers/watchdog/octeon-wdt-nmi.S +++ b/drivers/watchdog/octeon-wdt-nmi.S @@ -3,20 +3,40 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2007 Cavium Networks + * Copyright (C) 2007-2017 Cavium, Inc. */ #include <asm/asm.h> #include <asm/regdef.h> -#define SAVE_REG(r) sd $r, -32768+6912-(32-r)*8($0) +#define CVMSEG_BASE -32768 +#define CVMSEG_SIZE 6912 +#define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0) NESTED(octeon_wdt_nmi_stage2, 0, sp) .set push .set noreorder .set noat - /* Save all registers to the top CVMSEG. This shouldn't + /* Clear Dcache so cvmseg works right. */ + cache 1,0($0) + /* Use K0 to do a read/modify/write of CVMMEMCTL */ + dmfc0 k0, $11, 7 + /* Clear out the size of CVMSEG */ + dins k0, $0, 0, 6 + /* Set CVMSEG to its largest value */ + ori k0, k0, 0x1c0 | 54 + /* Store the CVMMEMCTL value */ + dmtc0 k0, $11, 7 + /* + * Restore K0 from the debug scratch register, it was saved in + * the boot-vector code. + */ + dmfc0 k0, $31 + + /* + * Save all registers to the top CVMSEG. This shouldn't * corrupt any state used by the kernel. Also all registers - * should have the value right before the NMI. */ + * should have the value right before the NMI. + */ SAVE_REG(0) SAVE_REG(1) SAVE_REG(2) @@ -49,16 +69,22 @@ SAVE_REG(29) SAVE_REG(30) SAVE_REG(31) + /* Write zero to all CVMSEG locations per Core-15169 */ + dli a0, CVMSEG_SIZE - (33 * 8) +1: sd zero, CVMSEG_BASE(a0) + daddiu a0, a0, -8 + bgez a0, 1b + nop /* Set the stack to begin right below the registers */ - li sp, -32768+6912-32*8 + dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8) /* Load the address of the third stage handler */ - dla a0, octeon_wdt_nmi_stage3 + dla $25, octeon_wdt_nmi_stage3 /* Call the third stage handler */ - jal a0 + jal $25 /* a0 is the address of the saved registers */ move a0, sp /* Loop forvever if we get here. */ -1: b 1b +2: b 2b nop .set pop END(octeon_wdt_nmi_stage2) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index fae7fe929ea3..1cf286945b7a 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -51,9 +51,16 @@ struct xwdt_device { static int xilinx_wdt_start(struct watchdog_device *wdd) { + int ret; u32 control_status_reg; struct xwdt_device *xdev = watchdog_get_drvdata(wdd); + ret = clk_enable(xdev->clk); + if (ret) { + dev_err(wdd->parent, "Failed to enable clock\n"); + return ret; + } + spin_lock(&xdev->spinlock); /* Clean previous status and enable the watchdog timer */ @@ -85,6 +92,9 @@ static int xilinx_wdt_stop(struct watchdog_device *wdd) iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); spin_unlock(&xdev->spinlock); + + clk_disable(xdev->clk); + pr_info("Stopped!\n"); return 0; @@ -167,11 +177,6 @@ static int xwdt_probe(struct platform_device *pdev) if (IS_ERR(xdev->base)) return PTR_ERR(xdev->base); - rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq); - if (rc) - dev_warn(&pdev->dev, - "The watchdog clock frequency cannot be obtained\n"); - rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval", &xdev->wdt_interval); if (rc) @@ -186,6 +191,26 @@ static int xwdt_probe(struct platform_device *pdev) watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); + xdev->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(xdev->clk)) { + if (PTR_ERR(xdev->clk) != -ENOENT) + return PTR_ERR(xdev->clk); + + /* + * Clock framework support is optional, continue on + * anyways if we don't find a matching clock. + */ + xdev->clk = NULL; + + rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", + &pfreq); + if (rc) + dev_warn(&pdev->dev, + "The watchdog clock freq cannot be obtained\n"); + } else { + pfreq = clk_get_rate(xdev->clk); + } + /* * Twice of the 2^wdt_interval / freq because the first wdt overflow is * ignored (interrupt), reset is only generated at second wdt overflow @@ -197,14 +222,6 @@ static int xwdt_probe(struct platform_device *pdev) spin_lock_init(&xdev->spinlock); watchdog_set_drvdata(xilinx_wdt_wdd, xdev); - xdev->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(xdev->clk)) { - if (PTR_ERR(xdev->clk) == -ENOENT) - xdev->clk = NULL; - else - return PTR_ERR(xdev->clk); - } - rc = clk_prepare_enable(xdev->clk); if (rc) { dev_err(&pdev->dev, "unable to enable clock\n"); @@ -223,6 +240,8 @@ static int xwdt_probe(struct platform_device *pdev) goto err_clk_disable; } + clk_disable(xdev->clk); + dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", xdev->base, xilinx_wdt_wdd->timeout); @@ -245,6 +264,43 @@ static int xwdt_remove(struct platform_device *pdev) return 0; } +/** + * xwdt_suspend - Suspend the device. + * + * @dev: handle to the device structure. + * Return: 0 always. + */ +static int __maybe_unused xwdt_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xwdt_device *xdev = platform_get_drvdata(pdev); + + if (watchdog_active(&xdev->xilinx_wdt_wdd)) + xilinx_wdt_stop(&xdev->xilinx_wdt_wdd); + + return 0; +} + +/** + * xwdt_resume - Resume the device. + * + * @dev: handle to the device structure. + * Return: 0 on success, errno otherwise. + */ +static int __maybe_unused xwdt_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xwdt_device *xdev = platform_get_drvdata(pdev); + int ret = 0; + + if (watchdog_active(&xdev->xilinx_wdt_wdd)) + ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd); + + return ret; +} + +static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume); + /* Match table for of_platform binding */ static const struct of_device_id xwdt_of_match[] = { { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, @@ -259,6 +315,7 @@ static struct platform_driver xwdt_driver = { .driver = { .name = WATCHDOG_NAME, .of_match_table = xwdt_of_match, + .pm = &xwdt_pm_ops, }, }; diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 5615f4013924..b9e376c8e2e3 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -74,7 +74,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" #define USB_PCWD_PRODUCT_ID 0x1140 /* table of devices that work with this driver */ -static struct usb_device_id usb_pcwd_table[] = { +static const struct usb_device_id usb_pcwd_table[] = { { USB_DEVICE(USB_PCWD_VENDOR_ID, USB_PCWD_PRODUCT_ID) }, { } /* Terminating entry */ }; diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index 4f47b5e90956..780971318810 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -162,6 +162,8 @@ static int qcom_wdt_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; /* We use CPU0's DGT for the watchdog */ if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c index cf61c92f7ecd..831ef83f6de1 100644 --- a/drivers/watchdog/renesas_wdt.c +++ b/drivers/watchdog/renesas_wdt.c @@ -1,8 +1,8 @@ /* * Watchdog driver for Renesas WDT watchdog * - * Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> - * Copyright (C) 2015-16 Renesas Electronics Corporation + * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> + * Copyright (C) 2015-17 Renesas Electronics Corporation * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by @@ -23,10 +23,22 @@ #define RWTCSRA_WOVF BIT(4) #define RWTCSRA_WRFLG BIT(5) #define RWTCSRA_TME BIT(7) +#define RWTCSRB 8 #define RWDT_DEFAULT_TIMEOUT 60U -static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024 }; +/* + * In probe, clk_rate is checked to be not more than 16 bit * biggest clock + * divider (12 bits). d is only a factor to fully utilize the WDT counter and + * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. + */ +#define MUL_BY_CLKS_PER_SEC(p, d) \ + DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) + +/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */ +#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) + +static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 }; static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); @@ -36,8 +48,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" struct rwdt_priv { void __iomem *base; struct watchdog_device wdev; - struct clk *clk; - unsigned int clks_per_sec; + unsigned long clk_rate; u8 cks; }; @@ -55,7 +66,7 @@ static int rwdt_init_timeout(struct watchdog_device *wdev) { struct rwdt_priv *priv = watchdog_get_drvdata(wdev); - rwdt_write(priv, 65536 - wdev->timeout * priv->clks_per_sec, RWTCNT); + rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); return 0; } @@ -64,8 +75,9 @@ static int rwdt_start(struct watchdog_device *wdev) { struct rwdt_priv *priv = watchdog_get_drvdata(wdev); - clk_prepare_enable(priv->clk); + pm_runtime_get_sync(wdev->parent); + rwdt_write(priv, 0, RWTCSRB); rwdt_write(priv, priv->cks, RWTCSRA); rwdt_init_timeout(wdev); @@ -82,7 +94,7 @@ static int rwdt_stop(struct watchdog_device *wdev) struct rwdt_priv *priv = watchdog_get_drvdata(wdev); rwdt_write(priv, priv->cks, RWTCSRA); - clk_disable_unprepare(priv->clk); + pm_runtime_put(wdev->parent); return 0; } @@ -92,7 +104,7 @@ static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev) struct rwdt_priv *priv = watchdog_get_drvdata(wdev); u16 val = readw_relaxed(priv->base + RWTCNT); - return DIV_ROUND_CLOSEST(65536 - val, priv->clks_per_sec); + return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); } static const struct watchdog_info rwdt_ident = { @@ -112,8 +124,8 @@ static int rwdt_probe(struct platform_device *pdev) { struct rwdt_priv *priv; struct resource *res; - unsigned long rate; - unsigned int clks_per_sec; + struct clk *clk; + unsigned long clks_per_sec; int ret, i; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); @@ -125,36 +137,40 @@ static int rwdt_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + pm_runtime_enable(&pdev->dev); - rate = clk_get_rate(priv->clk); - if (!rate) - return -ENOENT; + pm_runtime_get_sync(&pdev->dev); + priv->clk_rate = clk_get_rate(clk); + pm_runtime_put(&pdev->dev); + + if (!priv->clk_rate) { + ret = -ENOENT; + goto out_pm_disable; + } for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { - clks_per_sec = DIV_ROUND_UP(rate, clk_divs[i]); - if (clks_per_sec) { - priv->clks_per_sec = clks_per_sec; + clks_per_sec = priv->clk_rate / clk_divs[i]; + if (clks_per_sec && clks_per_sec < 65536) { priv->cks = i; break; } } - if (!clks_per_sec) { + if (i < 0) { dev_err(&pdev->dev, "Can't find suitable clock divider\n"); - return -ERANGE; + ret = -ERANGE; + goto out_pm_disable; } - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - priv->wdev.info = &rwdt_ident, priv->wdev.ops = &rwdt_ops, priv->wdev.parent = &pdev->dev; priv->wdev.min_timeout = 1; - priv->wdev.max_timeout = 65536 / clks_per_sec; + priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT); platform_set_drvdata(pdev, priv); @@ -167,13 +183,14 @@ static int rwdt_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n"); ret = watchdog_register_device(&priv->wdev); - if (ret < 0) { - pm_runtime_put(&pdev->dev); - pm_runtime_disable(&pdev->dev); - return ret; - } + if (ret < 0) + goto out_pm_disable; return 0; + + out_pm_disable: + pm_runtime_disable(&pdev->dev); + return ret; } static int rwdt_remove(struct platform_device *pdev) @@ -181,7 +198,6 @@ static int rwdt_remove(struct platform_device *pdev) struct rwdt_priv *priv = platform_get_drvdata(pdev); watchdog_unregister_device(&priv->wdev); - pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); return 0; diff --git a/drivers/watchdog/rt2880_wdt.c b/drivers/watchdog/rt2880_wdt.c index 05524baf7dcc..98967f0a7d10 100644 --- a/drivers/watchdog/rt2880_wdt.c +++ b/drivers/watchdog/rt2880_wdt.c @@ -119,7 +119,7 @@ static int rt288x_wdt_bootcause(void) return 0; } -static struct watchdog_info rt288x_wdt_info = { +static const struct watchdog_info rt288x_wdt_info = { .identity = "Ralink Watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, }; @@ -152,7 +152,7 @@ static int rt288x_wdt_probe(struct platform_device *pdev) if (IS_ERR(rt288x_wdt_clk)) return PTR_ERR(rt288x_wdt_clk); - rt288x_wdt_reset = devm_reset_control_get(&pdev->dev, NULL); + rt288x_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (!IS_ERR(rt288x_wdt_reset)) reset_control_deassert(rt288x_wdt_reset); diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index b34d3d5ba632..8e4e2fc13f87 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c @@ -342,7 +342,7 @@ static int __init sc1200wdt_probe(void) #if defined CONFIG_PNP -static struct pnp_device_id scl200wdt_pnp_devices[] = { +static const struct pnp_device_id scl200wdt_pnp_devices[] = { /* National Semiconductor PC87307/PC97307 watchdog component */ {.id = "NSC0800", .driver_data = 0}, {.id = ""}, diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index e7a715e82021..03805bc5d67a 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -281,7 +281,7 @@ static int __maybe_unused sp805_wdt_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, sp805_wdt_resume); -static struct amba_id sp805_wdt_ids[] = { +static const struct amba_id sp805_wdt_ids[] = { { .id = 0x00141805, .mask = 0x00ffffff, diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c index 6c501b7dba29..be64a8699de3 100644 --- a/drivers/watchdog/stm32_iwdg.c +++ b/drivers/watchdog/stm32_iwdg.c @@ -140,7 +140,7 @@ static const struct watchdog_info stm32_iwdg_info = { .identity = "STM32 Independent Watchdog", }; -static struct watchdog_ops stm32_iwdg_ops = { +static const struct watchdog_ops stm32_iwdg_ops = { .owner = THIS_MODULE, .start = stm32_iwdg_start, .ping = stm32_iwdg_ping, diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c index 17c25daebcce..811e43c39ec4 100644 --- a/drivers/watchdog/ts72xx_wdt.c +++ b/drivers/watchdog/ts72xx_wdt.c @@ -112,7 +112,7 @@ static const struct watchdog_info ts72xx_wdt_ident = { .identity = "TS-72XX WDT", }; -static struct watchdog_ops ts72xx_wdt_ops = { +static const struct watchdog_ops ts72xx_wdt_ops = { .owner = THIS_MODULE, .start = ts72xx_wdt_start, .stop = ts72xx_wdt_stop, diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index d9ba0496713c..7817836bff55 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -429,7 +429,7 @@ static int __init wdt_init(void) { int ret; int chip; - const char * const chip_name[] = { + static const char * const chip_name[] = { "W83627HF", "W83627S", "W83697HF", diff --git a/drivers/watchdog/ziirave_wdt.c b/drivers/watchdog/ziirave_wdt.c index b4e0cea5a64e..d3594aa3a374 100644 --- a/drivers/watchdog/ziirave_wdt.c +++ b/drivers/watchdog/ziirave_wdt.c @@ -737,7 +737,7 @@ static int ziirave_wdt_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id ziirave_wdt_id[] = { +static const struct i2c_device_id ziirave_wdt_id[] = { { "rave-wdt", 0 }, { } }; diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c index 69ec5855584b..9261f7c77f6d 100644 --- a/drivers/watchdog/zx2967_wdt.c +++ b/drivers/watchdog/zx2967_wdt.c @@ -229,7 +229,7 @@ static int zx2967_wdt_probe(struct platform_device *pdev) } clk_set_rate(wdt->clock, ZX2967_WDT_CLK_FREQ); - rstc = devm_reset_control_get(dev, NULL); + rstc = devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(rstc)) { dev_err(dev, "failed to get rstc"); ret = PTR_ERR(rstc); |