summaryrefslogtreecommitdiff
path: root/include/dt-bindings/clock
diff options
context:
space:
mode:
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/bcm-cygnus.h68
-rw-r--r--include/dt-bindings/clock/hi6220-clock.h173
-rw-r--r--include/dt-bindings/clock/lpc18xx-ccu.h74
-rw-r--r--include/dt-bindings/clock/lpc18xx-cgu.h41
-rw-r--r--include/dt-bindings/clock/marvell,mmp2.h1
-rw-r--r--include/dt-bindings/clock/marvell,pxa168.h3
-rw-r--r--include/dt-bindings/clock/marvell,pxa1928.h57
-rw-r--r--include/dt-bindings/clock/marvell,pxa910.h4
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h25
-rw-r--r--include/dt-bindings/clock/mt8135-clk.h194
-rw-r--r--include/dt-bindings/clock/mt8173-clk.h235
11 files changed, 875 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/bcm-cygnus.h b/include/dt-bindings/clock/bcm-cygnus.h
new file mode 100644
index 000000000000..32fbc475087a
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-cygnus.h
@@ -0,0 +1,68 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_CYGNUS_H
+#define _CLOCK_BCM_CYGNUS_H
+
+/* GENPLL clock ID */
+#define BCM_CYGNUS_GENPLL 0
+#define BCM_CYGNUS_GENPLL_AXI21_CLK 1
+#define BCM_CYGNUS_GENPLL_250MHZ_CLK 2
+#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 3
+#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 4
+#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 5
+#define BCM_CYGNUS_GENPLL_CAN_CLK 6
+
+/* LCPLL0 clock ID */
+#define BCM_CYGNUS_LCPLL0 0
+#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 1
+#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 2
+#define BCM_CYGNUS_LCPLL0_SDIO_CLK 3
+#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 4
+#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 5
+#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 6
+
+/* MIPI PLL clock ID */
+#define BCM_CYGNUS_MIPIPLL 0
+#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 1
+#define BCM_CYGNUS_MIPIPLL_CH1_LCD 2
+#define BCM_CYGNUS_MIPIPLL_CH2_V3D 3
+#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 4
+#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 5
+#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 6
+
+/* ASIU clock ID */
+#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0
+#define BCM_CYGNUS_ASIU_ADC_CLK 1
+#define BCM_CYGNUS_ASIU_PWM_CLK 2
+
+#endif /* _CLOCK_BCM_CYGNUS_H */
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
new file mode 100644
index 000000000000..70ee3833a7a0
--- /dev/null
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK 0
+
+/* fixed rate clocks */
+#define HI6220_REF32K 1
+#define HI6220_CLK_TCXO 2
+#define HI6220_MMC1_PAD 3
+#define HI6220_MMC2_PAD 4
+#define HI6220_MMC0_PAD 5
+#define HI6220_PLL_BBP 6
+#define HI6220_PLL_GPU 7
+#define HI6220_PLL1_DDR 8
+#define HI6220_PLL_SYS 9
+#define HI6220_PLL_SYS_MEDIA 10
+#define HI6220_DDR_SRC 11
+#define HI6220_PLL_MEDIA 12
+#define HI6220_PLL_DDR 13
+
+/* fixed factor clocks */
+#define HI6220_300M 14
+#define HI6220_150M 15
+#define HI6220_PICOPHY_SRC 16
+#define HI6220_MMC0_SRC_SEL 17
+#define HI6220_MMC1_SRC_SEL 18
+#define HI6220_MMC2_SRC_SEL 19
+#define HI6220_VPU_CODEC 20
+#define HI6220_MMC0_SMP 21
+#define HI6220_MMC1_SMP 22
+#define HI6220_MMC2_SMP 23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK 24
+#define HI6220_WDT1_PCLK 25
+#define HI6220_WDT2_PCLK 26
+#define HI6220_TIMER0_PCLK 27
+#define HI6220_TIMER1_PCLK 28
+#define HI6220_TIMER2_PCLK 29
+#define HI6220_TIMER3_PCLK 30
+#define HI6220_TIMER4_PCLK 31
+#define HI6220_TIMER5_PCLK 32
+#define HI6220_TIMER6_PCLK 33
+#define HI6220_TIMER7_PCLK 34
+#define HI6220_TIMER8_PCLK 35
+#define HI6220_UART0_PCLK 36
+
+#define HI6220_AO_NR_CLKS 37
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK 1
+#define HI6220_MMC0_CIUCLK 2
+#define HI6220_MMC1_CLK 3
+#define HI6220_MMC1_CIUCLK 4
+#define HI6220_MMC2_CLK 5
+#define HI6220_MMC2_CIUCLK 6
+#define HI6220_USBOTG_HCLK 7
+#define HI6220_CLK_PICOPHY 8
+#define HI6220_HIFI 9
+#define HI6220_DACODEC_PCLK 10
+#define HI6220_EDMAC_ACLK 11
+#define HI6220_CS_ATB 12
+#define HI6220_I2C0_CLK 13
+#define HI6220_I2C1_CLK 14
+#define HI6220_I2C2_CLK 15
+#define HI6220_I2C3_CLK 16
+#define HI6220_UART1_PCLK 17
+#define HI6220_UART2_PCLK 18
+#define HI6220_UART3_PCLK 19
+#define HI6220_UART4_PCLK 20
+#define HI6220_SPI_CLK 21
+#define HI6220_TSENSOR_CLK 22
+#define HI6220_MMU_CLK 23
+#define HI6220_HIFI_SEL 24
+#define HI6220_MMC0_SYSPLL 25
+#define HI6220_MMC1_SYSPLL 26
+#define HI6220_MMC2_SYSPLL 27
+#define HI6220_MMC0_SEL 28
+#define HI6220_MMC1_SEL 29
+#define HI6220_BBPPLL_SEL 30
+#define HI6220_MEDIA_PLL_SRC 31
+#define HI6220_MMC2_SEL 32
+#define HI6220_CS_ATB_SYSPLL 33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC 34
+#define HI6220_MMC0_SMP_IN 35
+#define HI6220_MMC1_SRC 36
+#define HI6220_MMC1_SMP_IN 37
+#define HI6220_MMC2_SRC 38
+#define HI6220_MMC2_SMP_IN 39
+#define HI6220_HIFI_SRC 40
+#define HI6220_UART1_SRC 41
+#define HI6220_UART2_SRC 42
+#define HI6220_UART3_SRC 43
+#define HI6220_UART4_SRC 44
+#define HI6220_MMC0_MUX0 45
+#define HI6220_MMC1_MUX0 46
+#define HI6220_MMC2_MUX0 47
+#define HI6220_MMC0_MUX1 48
+#define HI6220_MMC1_MUX1 49
+#define HI6220_MMC2_MUX1 50
+
+/* divider clocks */
+#define HI6220_CLK_BUS 51
+#define HI6220_MMC0_DIV 52
+#define HI6220_MMC1_DIV 53
+#define HI6220_MMC2_DIV 54
+#define HI6220_HIFI_DIV 55
+#define HI6220_BBPPLL0_DIV 56
+#define HI6220_CS_DAPB 57
+#define HI6220_CS_ATB_DIV 58
+
+#define HI6220_SYS_NR_CLKS 59
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK 1
+#define HI6220_G3D_PCLK 2
+#define HI6220_ACLK_CODEC_VPU 3
+#define HI6220_ISP_SCLK 4
+#define HI6220_ADE_CORE 5
+#define HI6220_MED_MMU 6
+#define HI6220_CFG_CSI4PHY 7
+#define HI6220_CFG_CSI2PHY 8
+#define HI6220_ISP_SCLK_GATE 9
+#define HI6220_ISP_SCLK_GATE1 10
+#define HI6220_ADE_CORE_GATE 11
+#define HI6220_CODEC_VPU_GATE 12
+#define HI6220_MED_SYSPLL 13
+
+/* mux clocks */
+#define HI6220_1440_1200 14
+#define HI6220_1000_1200 15
+#define HI6220_1000_1440 16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG 17
+#define HI6220_ISP_SCLK_SRC 18
+#define HI6220_ISP_SCLK1 19
+#define HI6220_ADE_CORE_SRC 20
+#define HI6220_ADE_PIX_SRC 21
+#define HI6220_G3D_CLK 22
+#define HI6220_CODEC_VPU_SRC 23
+
+#define HI6220_MEDIA_NR_CLKS 24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE 1
+#define HI6220_PLL1_DDR_GATE 2
+#define HI6220_PLL_DDR_GATE 3
+#define HI6220_PLL_MEDIA_GATE 4
+#define HI6220_PLL0_BBP_GATE 5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC 6
+#define HI6220_DDRC_AXI1 7
+
+#define HI6220_POWER_NR_CLKS 8
+#endif
diff --git a/include/dt-bindings/clock/lpc18xx-ccu.h b/include/dt-bindings/clock/lpc18xx-ccu.h
new file mode 100644
index 000000000000..bbfe00b6ab7d
--- /dev/null
+++ b/include/dt-bindings/clock/lpc18xx-ccu.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* Clock Control Unit 1 (CCU1) clock offsets */
+#define CLK_APB3_BUS 0x100
+#define CLK_APB3_I2C1 0x108
+#define CLK_APB3_DAC 0x110
+#define CLK_APB3_ADC0 0x118
+#define CLK_APB3_ADC1 0x120
+#define CLK_APB3_CAN0 0x128
+#define CLK_APB1_BUS 0x200
+#define CLK_APB1_MOTOCON_PWM 0x208
+#define CLK_APB1_I2C0 0x210
+#define CLK_APB1_I2S 0x218
+#define CLK_APB1_CAN1 0x220
+#define CLK_SPIFI 0x300
+#define CLK_CPU_BUS 0x400
+#define CLK_CPU_SPIFI 0x408
+#define CLK_CPU_GPIO 0x410
+#define CLK_CPU_LCD 0x418
+#define CLK_CPU_ETHERNET 0x420
+#define CLK_CPU_USB0 0x428
+#define CLK_CPU_EMC 0x430
+#define CLK_CPU_SDIO 0x438
+#define CLK_CPU_DMA 0x440
+#define CLK_CPU_CORE 0x448
+#define CLK_CPU_SCT 0x468
+#define CLK_CPU_USB1 0x470
+#define CLK_CPU_EMCDIV 0x478
+#define CLK_CPU_FLASHA 0x480
+#define CLK_CPU_FLASHB 0x488
+#define CLK_CPU_M0APP 0x490
+#define CLK_CPU_ADCHS 0x498
+#define CLK_CPU_EEPROM 0x4a0
+#define CLK_CPU_WWDT 0x500
+#define CLK_CPU_UART0 0x508
+#define CLK_CPU_UART1 0x510
+#define CLK_CPU_SSP0 0x518
+#define CLK_CPU_TIMER0 0x520
+#define CLK_CPU_TIMER1 0x528
+#define CLK_CPU_SCU 0x530
+#define CLK_CPU_CREG 0x538
+#define CLK_CPU_RITIMER 0x600
+#define CLK_CPU_UART2 0x608
+#define CLK_CPU_UART3 0x610
+#define CLK_CPU_TIMER2 0x618
+#define CLK_CPU_TIMER3 0x620
+#define CLK_CPU_SSP1 0x628
+#define CLK_CPU_QEI 0x630
+#define CLK_PERIPH_BUS 0x700
+#define CLK_PERIPH_CORE 0x710
+#define CLK_PERIPH_SGPIO 0x718
+#define CLK_USB0 0x800
+#define CLK_USB1 0x900
+#define CLK_SPI 0xA00
+#define CLK_ADCHS 0xB00
+
+/* Clock Control Unit 2 (CCU2) clock offsets */
+#define CLK_AUDIO 0x100
+#define CLK_APB2_UART3 0x200
+#define CLK_APB2_UART2 0x300
+#define CLK_APB0_UART1 0x400
+#define CLK_APB0_UART0 0x500
+#define CLK_APB2_SSP1 0x600
+#define CLK_APB0_SSP0 0x700
+#define CLK_SDIO 0x800
diff --git a/include/dt-bindings/clock/lpc18xx-cgu.h b/include/dt-bindings/clock/lpc18xx-cgu.h
new file mode 100644
index 000000000000..6e57c6d2ca66
--- /dev/null
+++ b/include/dt-bindings/clock/lpc18xx-cgu.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* LPC18xx/43xx base clock ids */
+#define BASE_SAFE_CLK 0
+#define BASE_USB0_CLK 1
+#define BASE_PERIPH_CLK 2
+#define BASE_USB1_CLK 3
+#define BASE_CPU_CLK 4
+#define BASE_SPIFI_CLK 5
+#define BASE_SPI_CLK 6
+#define BASE_PHY_RX_CLK 7
+#define BASE_PHY_TX_CLK 8
+#define BASE_APB1_CLK 9
+#define BASE_APB3_CLK 10
+#define BASE_LCD_CLK 11
+#define BASE_ADCHS_CLK 12
+#define BASE_SDIO_CLK 13
+#define BASE_SSP0_CLK 14
+#define BASE_SSP1_CLK 15
+#define BASE_UART0_CLK 16
+#define BASE_UART1_CLK 17
+#define BASE_UART2_CLK 18
+#define BASE_UART3_CLK 19
+#define BASE_OUT_CLK 20
+#define BASE_RES1_CLK 21
+#define BASE_RES2_CLK 22
+#define BASE_RES3_CLK 23
+#define BASE_RES4_CLK 24
+#define BASE_AUDIO_CLK 25
+#define BASE_CGU_OUT0_CLK 26
+#define BASE_CGU_OUT1_CLK 27
+#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1)
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index 591f7fba89e2..7a510384a82a 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -48,6 +48,7 @@
#define MMP2_CLK_SSP1 78
#define MMP2_CLK_SSP2 79
#define MMP2_CLK_SSP3 80
+#define MMP2_CLK_TIMER 81
/* axi periphrals */
#define MMP2_CLK_SDH0 101
diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h
index 79630b9d74b8..3e45bdfe1aa4 100644
--- a/include/dt-bindings/clock/marvell,pxa168.h
+++ b/include/dt-bindings/clock/marvell,pxa168.h
@@ -18,7 +18,9 @@
#define PXA168_CLK_PLL1_13_1_5 18
#define PXA168_CLK_PLL1_2_1_5 19
#define PXA168_CLK_PLL1_3_16 20
+#define PXA168_CLK_PLL1_192 21
#define PXA168_CLK_UART_PLL 27
+#define PXA168_CLK_USB_PLL 28
/* apb periphrals */
#define PXA168_CLK_TWSI0 60
@@ -40,6 +42,7 @@
#define PXA168_CLK_SSP2 76
#define PXA168_CLK_SSP3 77
#define PXA168_CLK_SSP4 78
+#define PXA168_CLK_TIMER 79
/* axi periphrals */
#define PXA168_CLK_DFC 100
diff --git a/include/dt-bindings/clock/marvell,pxa1928.h b/include/dt-bindings/clock/marvell,pxa1928.h
new file mode 100644
index 000000000000..d4f2e18919ff
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1928.h
@@ -0,0 +1,57 @@
+#ifndef __DTS_MARVELL_PXA1928_CLOCK_H
+#define __DTS_MARVELL_PXA1928_CLOCK_H
+
+/*
+ * Clock ID values here correspond to the control register offset/4.
+ */
+
+/* apb peripherals */
+#define PXA1928_CLK_RTC 0x00
+#define PXA1928_CLK_TWSI0 0x01
+#define PXA1928_CLK_TWSI1 0x02
+#define PXA1928_CLK_TWSI2 0x03
+#define PXA1928_CLK_TWSI3 0x04
+#define PXA1928_CLK_OWIRE 0x05
+#define PXA1928_CLK_KPC 0x06
+#define PXA1928_CLK_TB_ROTARY 0x07
+#define PXA1928_CLK_SW_JTAG 0x08
+#define PXA1928_CLK_TIMER1 0x09
+#define PXA1928_CLK_UART0 0x0b
+#define PXA1928_CLK_UART1 0x0c
+#define PXA1928_CLK_UART2 0x0d
+#define PXA1928_CLK_GPIO 0x0e
+#define PXA1928_CLK_PWM0 0x0f
+#define PXA1928_CLK_PWM1 0x10
+#define PXA1928_CLK_PWM2 0x11
+#define PXA1928_CLK_PWM3 0x12
+#define PXA1928_CLK_SSP0 0x13
+#define PXA1928_CLK_SSP1 0x14
+#define PXA1928_CLK_SSP2 0x15
+
+#define PXA1928_CLK_TWSI4 0x1f
+#define PXA1928_CLK_TWSI5 0x20
+#define PXA1928_CLK_UART3 0x22
+#define PXA1928_CLK_THSENS_GLOB 0x24
+#define PXA1928_CLK_THSENS_CPU 0x26
+#define PXA1928_CLK_THSENS_VPU 0x27
+#define PXA1928_CLK_THSENS_GC 0x28
+#define PXA1928_APBC_NR_CLKS 0x30
+
+
+/* axi peripherals */
+#define PXA1928_CLK_SDH0 0x15
+#define PXA1928_CLK_SDH1 0x16
+#define PXA1928_CLK_USB 0x17
+#define PXA1928_CLK_NAND 0x18
+#define PXA1928_CLK_DMA 0x19
+
+#define PXA1928_CLK_SDH2 0x3a
+#define PXA1928_CLK_SDH3 0x3b
+#define PXA1928_CLK_HSIC 0x3e
+#define PXA1928_CLK_SDH4 0x57
+#define PXA1928_CLK_GC3D 0x5d
+#define PXA1928_CLK_GC2D 0x5f
+
+#define PXA1928_APMU_NR_CLKS 0x60
+
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h
index 719cffb2bea2..135082a0b62f 100644
--- a/include/dt-bindings/clock/marvell,pxa910.h
+++ b/include/dt-bindings/clock/marvell,pxa910.h
@@ -18,7 +18,9 @@
#define PXA910_CLK_PLL1_13_1_5 18
#define PXA910_CLK_PLL1_2_1_5 19
#define PXA910_CLK_PLL1_3_16 20
+#define PXA910_CLK_PLL1_192 21
#define PXA910_CLK_UART_PLL 27
+#define PXA910_CLK_USB_PLL 28
/* apb periphrals */
#define PXA910_CLK_TWSI0 60
@@ -37,6 +39,8 @@
#define PXA910_CLK_UART2 73
#define PXA910_CLK_SSP0 74
#define PXA910_CLK_SSP1 75
+#define PXA910_CLK_TIMER0 76
+#define PXA910_CLK_TIMER1 77
/* axi periphrals */
#define PXA910_CLK_DFC 100
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
new file mode 100644
index 000000000000..bd2720d58e0c
--- /dev/null
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -0,0 +1,25 @@
+/*
+ * Meson8b clock tree IDs
+ */
+
+#ifndef __MESON8B_CLKC_H
+#define __MESON8B_CLKC_H
+
+#define CLKID_UNUSED 0
+#define CLKID_XTAL 1
+#define CLKID_PLL_FIXED 2
+#define CLKID_PLL_VID 3
+#define CLKID_PLL_SYS 4
+#define CLKID_FCLK_DIV2 5
+#define CLKID_FCLK_DIV3 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_CLK81 10
+#define CLKID_MALI 11
+#define CLKID_CPUCLK 12
+#define CLKID_ZERO 13
+
+#define CLK_NR_CLKS (CLKID_ZERO + 1)
+
+#endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/clock/mt8135-clk.h b/include/dt-bindings/clock/mt8135-clk.h
new file mode 100644
index 000000000000..6dac6c091dd2
--- /dev/null
+++ b/include/dt-bindings/clock/mt8135-clk.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8135_H
+#define _DT_BINDINGS_CLK_MT8135_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_DSI0_LNTC_DSICLK 1
+#define CLK_TOP_HDMITX_CLKDIG_CTS 2
+#define CLK_TOP_CLKPH_MCK 3
+#define CLK_TOP_CPUM_TCK_IN 4
+#define CLK_TOP_MAINPLL_806M 5
+#define CLK_TOP_MAINPLL_537P3M 6
+#define CLK_TOP_MAINPLL_322P4M 7
+#define CLK_TOP_MAINPLL_230P3M 8
+#define CLK_TOP_UNIVPLL_624M 9
+#define CLK_TOP_UNIVPLL_416M 10
+#define CLK_TOP_UNIVPLL_249P6M 11
+#define CLK_TOP_UNIVPLL_178P3M 12
+#define CLK_TOP_UNIVPLL_48M 13
+#define CLK_TOP_MMPLL_D2 14
+#define CLK_TOP_MMPLL_D3 15
+#define CLK_TOP_MMPLL_D5 16
+#define CLK_TOP_MMPLL_D7 17
+#define CLK_TOP_MMPLL_D4 18
+#define CLK_TOP_MMPLL_D6 19
+#define CLK_TOP_SYSPLL_D2 20
+#define CLK_TOP_SYSPLL_D4 21
+#define CLK_TOP_SYSPLL_D6 22
+#define CLK_TOP_SYSPLL_D8 23
+#define CLK_TOP_SYSPLL_D10 24
+#define CLK_TOP_SYSPLL_D12 25
+#define CLK_TOP_SYSPLL_D16 26
+#define CLK_TOP_SYSPLL_D24 27
+#define CLK_TOP_SYSPLL_D3 28
+#define CLK_TOP_SYSPLL_D2P5 29
+#define CLK_TOP_SYSPLL_D5 30
+#define CLK_TOP_SYSPLL_D3P5 31
+#define CLK_TOP_UNIVPLL1_D2 32
+#define CLK_TOP_UNIVPLL1_D4 33
+#define CLK_TOP_UNIVPLL1_D6 34
+#define CLK_TOP_UNIVPLL1_D8 35
+#define CLK_TOP_UNIVPLL1_D10 36
+#define CLK_TOP_UNIVPLL2_D2 37
+#define CLK_TOP_UNIVPLL2_D4 38
+#define CLK_TOP_UNIVPLL2_D6 39
+#define CLK_TOP_UNIVPLL2_D8 40
+#define CLK_TOP_UNIVPLL_D3 41
+#define CLK_TOP_UNIVPLL_D5 42
+#define CLK_TOP_UNIVPLL_D7 43
+#define CLK_TOP_UNIVPLL_D10 44
+#define CLK_TOP_UNIVPLL_D26 45
+#define CLK_TOP_APLL 46
+#define CLK_TOP_APLL_D4 47
+#define CLK_TOP_APLL_D8 48
+#define CLK_TOP_APLL_D16 49
+#define CLK_TOP_APLL_D24 50
+#define CLK_TOP_LVDSPLL_D2 51
+#define CLK_TOP_LVDSPLL_D4 52
+#define CLK_TOP_LVDSPLL_D8 53
+#define CLK_TOP_LVDSTX_CLKDIG_CT 54
+#define CLK_TOP_VPLL_DPIX 55
+#define CLK_TOP_TVHDMI_H 56
+#define CLK_TOP_HDMITX_CLKDIG_D2 57
+#define CLK_TOP_HDMITX_CLKDIG_D3 58
+#define CLK_TOP_TVHDMI_D2 59
+#define CLK_TOP_TVHDMI_D4 60
+#define CLK_TOP_MEMPLL_MCK_D4 61
+#define CLK_TOP_AXI_SEL 62
+#define CLK_TOP_SMI_SEL 63
+#define CLK_TOP_MFG_SEL 64
+#define CLK_TOP_IRDA_SEL 65
+#define CLK_TOP_CAM_SEL 66
+#define CLK_TOP_AUD_INTBUS_SEL 67
+#define CLK_TOP_JPG_SEL 68
+#define CLK_TOP_DISP_SEL 69
+#define CLK_TOP_MSDC30_1_SEL 70
+#define CLK_TOP_MSDC30_2_SEL 71
+#define CLK_TOP_MSDC30_3_SEL 72
+#define CLK_TOP_MSDC30_4_SEL 73
+#define CLK_TOP_USB20_SEL 74
+#define CLK_TOP_VENC_SEL 75
+#define CLK_TOP_SPI_SEL 76
+#define CLK_TOP_UART_SEL 77
+#define CLK_TOP_MEM_SEL 78
+#define CLK_TOP_CAMTG_SEL 79
+#define CLK_TOP_AUDIO_SEL 80
+#define CLK_TOP_FIX_SEL 81
+#define CLK_TOP_VDEC_SEL 82
+#define CLK_TOP_DDRPHYCFG_SEL 83
+#define CLK_TOP_DPILVDS_SEL 84
+#define CLK_TOP_PMICSPI_SEL 85
+#define CLK_TOP_MSDC30_0_SEL 86
+#define CLK_TOP_SMI_MFG_AS_SEL 87
+#define CLK_TOP_GCPU_SEL 88
+#define CLK_TOP_DPI1_SEL 89
+#define CLK_TOP_CCI_SEL 90
+#define CLK_TOP_APLL_SEL 91
+#define CLK_TOP_HDMIPLL_SEL 92
+#define CLK_TOP_NR_CLK 93
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMPLL1 1
+#define CLK_APMIXED_ARMPLL2 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIVPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_MSDCPLL 6
+#define CLK_APMIXED_TVDPLL 7
+#define CLK_APMIXED_LVDSPLL 8
+#define CLK_APMIXED_AUDPLL 9
+#define CLK_APMIXED_VDECPLL 10
+#define CLK_APMIXED_NR_CLK 11
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_PMIC_WRAP 1
+#define CLK_INFRA_PMICSPI 2
+#define CLK_INFRA_CCIF1_AP_CTRL 3
+#define CLK_INFRA_CCIF0_AP_CTRL 4
+#define CLK_INFRA_KP 5
+#define CLK_INFRA_CPUM 6
+#define CLK_INFRA_M4U 7
+#define CLK_INFRA_MFGAXI 8
+#define CLK_INFRA_DEVAPC 9
+#define CLK_INFRA_AUDIO 10
+#define CLK_INFRA_MFG_BUS 11
+#define CLK_INFRA_SMI 12
+#define CLK_INFRA_DBGCLK 13
+#define CLK_INFRA_NR_CLK 14
+
+/* PERI_SYS */
+
+#define CLK_PERI_I2C5 1
+#define CLK_PERI_I2C4 2
+#define CLK_PERI_I2C3 3
+#define CLK_PERI_I2C2 4
+#define CLK_PERI_I2C1 5
+#define CLK_PERI_I2C0 6
+#define CLK_PERI_UART3 7
+#define CLK_PERI_UART2 8
+#define CLK_PERI_UART1 9
+#define CLK_PERI_UART0 10
+#define CLK_PERI_IRDA 11
+#define CLK_PERI_NLI 12
+#define CLK_PERI_MD_HIF 13
+#define CLK_PERI_AP_HIF 14
+#define CLK_PERI_MSDC30_3 15
+#define CLK_PERI_MSDC30_2 16
+#define CLK_PERI_MSDC30_1 17
+#define CLK_PERI_MSDC20_2 18
+#define CLK_PERI_MSDC20_1 19
+#define CLK_PERI_AP_DMA 20
+#define CLK_PERI_USB1 21
+#define CLK_PERI_USB0 22
+#define CLK_PERI_PWM 23
+#define CLK_PERI_PWM7 24
+#define CLK_PERI_PWM6 25
+#define CLK_PERI_PWM5 26
+#define CLK_PERI_PWM4 27
+#define CLK_PERI_PWM3 28
+#define CLK_PERI_PWM2 29
+#define CLK_PERI_PWM1 30
+#define CLK_PERI_THERM 31
+#define CLK_PERI_NFI 32
+#define CLK_PERI_USBSLV 33
+#define CLK_PERI_USB1_MCU 34
+#define CLK_PERI_USB0_MCU 35
+#define CLK_PERI_GCPU 36
+#define CLK_PERI_FHCTL 37
+#define CLK_PERI_SPI1 38
+#define CLK_PERI_AUXADC 39
+#define CLK_PERI_PERI_PWRAP 40
+#define CLK_PERI_I2C6 41
+#define CLK_PERI_UART0_SEL 42
+#define CLK_PERI_UART1_SEL 43
+#define CLK_PERI_UART2_SEL 44
+#define CLK_PERI_UART3_SEL 45
+#define CLK_PERI_NR_CLK 46
+
+#endif /* _DT_BINDINGS_CLK_MT8135_H */
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
new file mode 100644
index 000000000000..4ad76ed882ad
--- /dev/null
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8173_H
+#define _DT_BINDINGS_CLK_MT8173_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLKPH_MCK_O 1
+#define CLK_TOP_DPI 2
+#define CLK_TOP_USB_SYSPLL_125M 3
+#define CLK_TOP_HDMITX_DIG_CTS 4
+#define CLK_TOP_ARMCA7PLL_754M 5
+#define CLK_TOP_ARMCA7PLL_502M 6
+#define CLK_TOP_MAIN_H546M 7
+#define CLK_TOP_MAIN_H364M 8
+#define CLK_TOP_MAIN_H218P4M 9
+#define CLK_TOP_MAIN_H156M 10
+#define CLK_TOP_TVDPLL_445P5M 11
+#define CLK_TOP_TVDPLL_594M 12
+#define CLK_TOP_UNIV_624M 13
+#define CLK_TOP_UNIV_416M 14
+#define CLK_TOP_UNIV_249P6M 15
+#define CLK_TOP_UNIV_178P3M 16
+#define CLK_TOP_UNIV_48M 17
+#define CLK_TOP_CLKRTC_EXT 18
+#define CLK_TOP_CLKRTC_INT 19
+#define CLK_TOP_FPC 20
+#define CLK_TOP_HDMITXPLL_D2 21
+#define CLK_TOP_HDMITXPLL_D3 22
+#define CLK_TOP_ARMCA7PLL_D2 23
+#define CLK_TOP_ARMCA7PLL_D3 24
+#define CLK_TOP_APLL1 25
+#define CLK_TOP_APLL2 26
+#define CLK_TOP_DMPLL 27
+#define CLK_TOP_DMPLL_D2 28
+#define CLK_TOP_DMPLL_D4 29
+#define CLK_TOP_DMPLL_D8 30
+#define CLK_TOP_DMPLL_D16 31
+#define CLK_TOP_LVDSPLL_D2 32
+#define CLK_TOP_LVDSPLL_D4 33
+#define CLK_TOP_LVDSPLL_D8 34
+#define CLK_TOP_MMPLL 35
+#define CLK_TOP_MMPLL_D2 36
+#define CLK_TOP_MSDCPLL 37
+#define CLK_TOP_MSDCPLL_D2 38
+#define CLK_TOP_MSDCPLL_D4 39
+#define CLK_TOP_MSDCPLL2 40
+#define CLK_TOP_MSDCPLL2_D2 41
+#define CLK_TOP_MSDCPLL2_D4 42
+#define CLK_TOP_SYSPLL_D2 43
+#define CLK_TOP_SYSPLL1_D2 44
+#define CLK_TOP_SYSPLL1_D4 45
+#define CLK_TOP_SYSPLL1_D8 46
+#define CLK_TOP_SYSPLL1_D16 47
+#define CLK_TOP_SYSPLL_D3 48
+#define CLK_TOP_SYSPLL2_D2 49
+#define CLK_TOP_SYSPLL2_D4 50
+#define CLK_TOP_SYSPLL_D5 51
+#define CLK_TOP_SYSPLL3_D2 52
+#define CLK_TOP_SYSPLL3_D4 53
+#define CLK_TOP_SYSPLL_D7 54
+#define CLK_TOP_SYSPLL4_D2 55
+#define CLK_TOP_SYSPLL4_D4 56
+#define CLK_TOP_TVDPLL 57
+#define CLK_TOP_TVDPLL_D2 58
+#define CLK_TOP_TVDPLL_D4 59
+#define CLK_TOP_TVDPLL_D8 60
+#define CLK_TOP_TVDPLL_D16 61
+#define CLK_TOP_UNIVPLL_D2 62
+#define CLK_TOP_UNIVPLL1_D2 63
+#define CLK_TOP_UNIVPLL1_D4 64
+#define CLK_TOP_UNIVPLL1_D8 65
+#define CLK_TOP_UNIVPLL_D3 66
+#define CLK_TOP_UNIVPLL2_D2 67
+#define CLK_TOP_UNIVPLL2_D4 68
+#define CLK_TOP_UNIVPLL2_D8 69
+#define CLK_TOP_UNIVPLL_D5 70
+#define CLK_TOP_UNIVPLL3_D2 71
+#define CLK_TOP_UNIVPLL3_D4 72
+#define CLK_TOP_UNIVPLL3_D8 73
+#define CLK_TOP_UNIVPLL_D7 74
+#define CLK_TOP_UNIVPLL_D26 75
+#define CLK_TOP_UNIVPLL_D52 76
+#define CLK_TOP_VCODECPLL 77
+#define CLK_TOP_VCODECPLL_370P5 78
+#define CLK_TOP_VENCPLL 79
+#define CLK_TOP_VENCPLL_D2 80
+#define CLK_TOP_VENCPLL_D4 81
+#define CLK_TOP_AXI_SEL 82
+#define CLK_TOP_MEM_SEL 83
+#define CLK_TOP_DDRPHYCFG_SEL 84
+#define CLK_TOP_MM_SEL 85
+#define CLK_TOP_PWM_SEL 86
+#define CLK_TOP_VDEC_SEL 87
+#define CLK_TOP_VENC_SEL 88
+#define CLK_TOP_MFG_SEL 89
+#define CLK_TOP_CAMTG_SEL 90
+#define CLK_TOP_UART_SEL 91
+#define CLK_TOP_SPI_SEL 92
+#define CLK_TOP_USB20_SEL 93
+#define CLK_TOP_USB30_SEL 94
+#define CLK_TOP_MSDC50_0_H_SEL 95
+#define CLK_TOP_MSDC50_0_SEL 96
+#define CLK_TOP_MSDC30_1_SEL 97
+#define CLK_TOP_MSDC30_2_SEL 98
+#define CLK_TOP_MSDC30_3_SEL 99
+#define CLK_TOP_AUDIO_SEL 100
+#define CLK_TOP_AUD_INTBUS_SEL 101
+#define CLK_TOP_PMICSPI_SEL 102
+#define CLK_TOP_SCP_SEL 103
+#define CLK_TOP_ATB_SEL 104
+#define CLK_TOP_VENC_LT_SEL 105
+#define CLK_TOP_DPI0_SEL 106
+#define CLK_TOP_IRDA_SEL 107
+#define CLK_TOP_CCI400_SEL 108
+#define CLK_TOP_AUD_1_SEL 109
+#define CLK_TOP_AUD_2_SEL 110
+#define CLK_TOP_MEM_MFG_IN_SEL 111
+#define CLK_TOP_AXI_MFG_IN_SEL 112
+#define CLK_TOP_SCAM_SEL 113
+#define CLK_TOP_SPINFI_IFR_SEL 114
+#define CLK_TOP_HDMI_SEL 115
+#define CLK_TOP_DPILVDS_SEL 116
+#define CLK_TOP_MSDC50_2_H_SEL 117
+#define CLK_TOP_HDCP_SEL 118
+#define CLK_TOP_HDCP_24M_SEL 119
+#define CLK_TOP_RTC_SEL 120
+#define CLK_TOP_APLL1_DIV0 121
+#define CLK_TOP_APLL1_DIV1 122
+#define CLK_TOP_APLL1_DIV2 123
+#define CLK_TOP_APLL1_DIV3 124
+#define CLK_TOP_APLL1_DIV4 125
+#define CLK_TOP_APLL1_DIV5 126
+#define CLK_TOP_APLL2_DIV0 127
+#define CLK_TOP_APLL2_DIV1 128
+#define CLK_TOP_APLL2_DIV2 129
+#define CLK_TOP_APLL2_DIV3 130
+#define CLK_TOP_APLL2_DIV4 131
+#define CLK_TOP_APLL2_DIV5 132
+#define CLK_TOP_I2S0_M_SEL 133
+#define CLK_TOP_I2S1_M_SEL 134
+#define CLK_TOP_I2S2_M_SEL 135
+#define CLK_TOP_I2S3_M_SEL 136
+#define CLK_TOP_I2S3_B_SEL 137
+#define CLK_TOP_NR_CLK 138
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMCA15PLL 1
+#define CLK_APMIXED_ARMCA7PLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIVPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_MSDCPLL 6
+#define CLK_APMIXED_VENCPLL 7
+#define CLK_APMIXED_TVDPLL 8
+#define CLK_APMIXED_MPLL 9
+#define CLK_APMIXED_VCODECPLL 10
+#define CLK_APMIXED_APLL1 11
+#define CLK_APMIXED_APLL2 12
+#define CLK_APMIXED_LVDSPLL 13
+#define CLK_APMIXED_MSDCPLL2 14
+#define CLK_APMIXED_NR_CLK 15
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_DBGCLK 1
+#define CLK_INFRA_SMI 2
+#define CLK_INFRA_AUDIO 3
+#define CLK_INFRA_GCE 4
+#define CLK_INFRA_L2C_SRAM 5
+#define CLK_INFRA_M4U 6
+#define CLK_INFRA_CPUM 7
+#define CLK_INFRA_KP 8
+#define CLK_INFRA_CEC 9
+#define CLK_INFRA_PMICSPI 10
+#define CLK_INFRA_PMICWRAP 11
+#define CLK_INFRA_NR_CLK 12
+
+/* PERI_SYS */
+
+#define CLK_PERI_NFI 1
+#define CLK_PERI_THERM 2
+#define CLK_PERI_PWM1 3
+#define CLK_PERI_PWM2 4
+#define CLK_PERI_PWM3 5
+#define CLK_PERI_PWM4 6
+#define CLK_PERI_PWM5 7
+#define CLK_PERI_PWM6 8
+#define CLK_PERI_PWM7 9
+#define CLK_PERI_PWM 10
+#define CLK_PERI_USB0 11
+#define CLK_PERI_USB1 12
+#define CLK_PERI_AP_DMA 13
+#define CLK_PERI_MSDC30_0 14
+#define CLK_PERI_MSDC30_1 15
+#define CLK_PERI_MSDC30_2 16
+#define CLK_PERI_MSDC30_3 17
+#define CLK_PERI_NLI_ARB 18
+#define CLK_PERI_IRDA 19
+#define CLK_PERI_UART0 20
+#define CLK_PERI_UART1 21
+#define CLK_PERI_UART2 22
+#define CLK_PERI_UART3 23
+#define CLK_PERI_I2C0 24
+#define CLK_PERI_I2C1 25
+#define CLK_PERI_I2C2 26
+#define CLK_PERI_I2C3 27
+#define CLK_PERI_I2C4 28
+#define CLK_PERI_AUXADC 29
+#define CLK_PERI_SPI0 30
+#define CLK_PERI_I2C5 31
+#define CLK_PERI_NFIECC 32
+#define CLK_PERI_SPI 33
+#define CLK_PERI_IRRX 34
+#define CLK_PERI_I2C6 35
+#define CLK_PERI_UART0_SEL 36
+#define CLK_PERI_UART1_SEL 37
+#define CLK_PERI_UART2_SEL 38
+#define CLK_PERI_UART3_SEL 39
+#define CLK_PERI_NR_CLK 40
+
+#endif /* _DT_BINDINGS_CLK_MT8173_H */