diff options
Diffstat (limited to 'include/dt-bindings')
25 files changed, 825 insertions, 13 deletions
diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..b46732361b25 --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 6f66f9005c81..38145bdcd975 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -49,6 +49,7 @@ #define IMX7ULP_CLK_NIC1_DIV 36 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 +/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ #define IMX7ULP_CLK_MIPI_PLL 39 #define IMX7ULP_CLK_SIRC 40 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c686f3ef..edeece2289f0 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,23 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_END 246 #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index d7b201652f4c..0f2b8423ce1d 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -211,6 +211,23 @@ #define IMX8MN_CLK_GPU_CORE_ROOT 193 #define IMX8MN_CLK_GIC 194 -#define IMX8MN_CLK_END 195 +#define IMX8MN_SYS_PLL1_40M_CG 195 +#define IMX8MN_SYS_PLL1_80M_CG 196 +#define IMX8MN_SYS_PLL1_100M_CG 197 +#define IMX8MN_SYS_PLL1_133M_CG 198 +#define IMX8MN_SYS_PLL1_160M_CG 199 +#define IMX8MN_SYS_PLL1_200M_CG 200 +#define IMX8MN_SYS_PLL1_266M_CG 201 +#define IMX8MN_SYS_PLL1_400M_CG 202 +#define IMX8MN_SYS_PLL2_50M_CG 203 +#define IMX8MN_SYS_PLL2_100M_CG 204 +#define IMX8MN_SYS_PLL2_125M_CG 205 +#define IMX8MN_SYS_PLL2_166M_CG 206 +#define IMX8MN_SYS_PLL2_200M_CG 207 +#define IMX8MN_SYS_PLL2_250M_CG 208 +#define IMX8MN_SYS_PLL2_333M_CG 209 +#define IMX8MN_SYS_PLL2_500M_CG 210 + +#define IMX8MN_CLK_END 211 #endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 65463673d25e..3bab9b21c8d7 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -403,5 +403,27 @@ #define IMX8MQ_CLK_SNVS_ROOT 264 #define IMX8MQ_CLK_GIC 265 -#define IMX8MQ_CLK_END 266 +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 + +#define IMX8MQ_SYS1_PLL_40M_CG 267 +#define IMX8MQ_SYS1_PLL_80M_CG 268 +#define IMX8MQ_SYS1_PLL_100M_CG 269 +#define IMX8MQ_SYS1_PLL_133M_CG 270 +#define IMX8MQ_SYS1_PLL_160M_CG 271 +#define IMX8MQ_SYS1_PLL_200M_CG 272 +#define IMX8MQ_SYS1_PLL_266M_CG 273 +#define IMX8MQ_SYS1_PLL_400M_CG 274 +#define IMX8MQ_SYS1_PLL_800M_CG 275 +#define IMX8MQ_SYS2_PLL_50M_CG 276 +#define IMX8MQ_SYS2_PLL_100M_CG 277 +#define IMX8MQ_SYS2_PLL_125M_CG 278 +#define IMX8MQ_SYS2_PLL_166M_CG 279 +#define IMX8MQ_SYS2_PLL_200M_CG 280 +#define IMX8MQ_SYS2_PLL_250M_CG 281 +#define IMX8MQ_SYS2_PLL_333M_CG 282 +#define IMX8MQ_SYS2_PLL_500M_CG 283 +#define IMX8MQ_SYS2_PLL_1000M_CG 284 + +#define IMX8MQ_CLK_END 285 + #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index e5411938983c..ba672064ccb4 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -86,6 +86,10 @@ #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +/* iva clocks */ +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + /* dss clocks */ #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h index 00101479f7c4..5b1416fcde6f 100644 --- a/include/dt-bindings/clock/px30-cru.h +++ b/include/dt-bindings/clock/px30-cru.h @@ -85,6 +85,8 @@ #define SCLK_EMMC_DIV50 83 #define SCLK_DDRCLK 84 #define SCLK_UART1_SRC 85 +#define SCLK_SDMMC_DIV 86 +#define SCLK_SDMMC_DIV50 87 /* dclk gates */ #define DCLK_VOPB 150 diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index ab376262fcea..de1d8a1f5966 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -177,6 +177,11 @@ #define GCC_UFS_CLKREF_CLK 168 #define GCC_PCIE_CLKREF_CLK 169 #define GCC_RX1_USB2_CLKREF_CLK 170 +#define GCC_MSS_CFG_AHB_CLK 171 +#define GCC_BOOT_ROM_AHB_CLK 172 +#define GCC_MSS_GPLL0_DIV_CLK_SRC 173 +#define GCC_MSS_SNOC_AXI_CLK 174 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 175 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 @@ -290,5 +295,6 @@ #define GCC_MSMPU_BCR 105 #define GCC_QUSB2PHY_PRIM_BCR 106 #define GCC_QUSB2PHY_SEC_BCR 107 +#define GCC_MSS_RESTART 108 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h new file mode 100644 index 000000000000..e8029b2e92d7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H + +/* GCC clocks */ +#define GCC_GPLL0_MAIN_DIV_CDIV 0 +#define GPLL0 1 +#define GPLL0_OUT_EVEN 2 +#define GPLL1 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL7 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CE1_AHB_CLK 14 +#define GCC_CE1_AXI_CLK 15 +#define GCC_CE1_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CPUSS_AHB_CLK 18 +#define GCC_CPUSS_AHB_CLK_SRC 19 +#define GCC_CPUSS_GNOC_CLK 20 +#define GCC_CPUSS_RBCPR_CLK 21 +#define GCC_DDRSS_GPU_AXI_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_GPLL0_CLK_SRC 24 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPU_CFG_AHB_CLK 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AXI_CLK 40 +#define GCC_NPU_BWMON_AXI_CLK 41 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +#define GCC_NPU_CFG_AHB_CLK 44 +#define GCC_NPU_DMA_CLK 45 +#define GCC_NPU_GPLL0_CLK_SRC 46 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +#define GCC_PDM2_CLK 48 +#define GCC_PDM2_CLK_SRC 49 +#define GCC_PDM_AHB_CLK 50 +#define GCC_PDM_XO4_CLK 51 +#define GCC_PRNG_AHB_CLK 52 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +#define GCC_QSPI_CORE_CLK 54 +#define GCC_QSPI_CORE_CLK_SRC 55 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +#define GCC_QUPV3_WRAP0_CORE_CLK 57 +#define GCC_QUPV3_WRAP0_S0_CLK 58 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S1_CLK 60 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S2_CLK 62 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S3_CLK 64 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S4_CLK 66 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S5_CLK 68 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_CLK 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +#define GCC_SDCC1_AHB_CLK 88 +#define GCC_SDCC1_APPS_CLK 89 +#define GCC_SDCC1_APPS_CLK_SRC 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_SDCC2_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_MEM_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_SLEEP_CLK 113 +#define GCC_USB3_PRIM_CLKREF_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +#define GCC_VIDEO_XO_CLK 124 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB3_DP_PHY_PRIM_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3_PHY_PRIM_BCR 6 +#define GCC_USB3_PHY_SEC_BCR 7 +#define GCC_USB3PHY_PHY_PRIM_BCR 8 +#define GCC_USB3PHY_PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 + +/* GCC GDSCRs */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h new file mode 100644 index 000000000000..c6f5290f0914 --- /dev/null +++ b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H + +#define LCC_AHBFABRIC_CBC_CLK 0 +#define LCC_Q6SS_AHBS_CBC_CLK 1 +#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 +#define LCC_Q6SS_AHBM_CBC_CLK 3 +#define LCC_Q6SS_AXIM_CBC_CLK 4 +#define LCC_Q6SS_BCR_SLEEP_CLK 5 +#define TCSR_Q6SS_LCC_CBCR_CLK 6 + +#define Q6SSTOP_BCR_RESET 1 +#endif diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index c5f7e9a70968..30d2d15373a2 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -143,7 +143,7 @@ #define CLK_AVS 110 #define CLK_HDMI 111 #define CLK_HDMI_DDC 112 - +#define CLK_MBUS 113 #define CLK_GPU 114 /* New clocks imported in H5 */ diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 0bfbfc912c68..44f60623f99b 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,8 +308,8 @@ #define TEGRA210_CLK_CLK_OUT_2 278 #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 -/* 281 */ -#define TEGRA210_CLK_SOR1_SRC 282 +#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ +#define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 @@ -391,8 +391,7 @@ #define TEGRA210_CLK_CLK_OUT_3_MUX 358 #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */ -#define TEGRA210_CLK_SOR0_OUT 361 +/* 361 */ #define TEGRA210_CLK_XUSB_SS_DIV2 362 #define TEGRA210_CLK_PLL_M_UD 363 diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h new file mode 100644 index 000000000000..bbaebaf7adb9 --- /dev/null +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ + +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_SCLKA 4 +#define X1000_CLK_CPUMUX 5 +#define X1000_CLK_CPU 6 +#define X1000_CLK_L2CACHE 7 +#define X1000_CLK_AHB0 8 +#define X1000_CLK_AHB2PMUX 9 +#define X1000_CLK_AHB2 10 +#define X1000_CLK_PCLK 11 +#define X1000_CLK_DDR 12 +#define X1000_CLK_MAC 13 +#define X1000_CLK_MSCMUX 14 +#define X1000_CLK_MSC0 15 +#define X1000_CLK_MSC1 16 +#define X1000_CLK_SSIPLL 17 +#define X1000_CLK_SSIMUX 18 +#define X1000_CLK_SFC 19 +#define X1000_CLK_I2C0 20 +#define X1000_CLK_I2C1 21 +#define X1000_CLK_I2C2 22 +#define X1000_CLK_UART0 23 +#define X1000_CLK_UART1 24 +#define X1000_CLK_UART2 25 +#define X1000_CLK_SSI 26 +#define X1000_CLK_PDMA 27 + +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/dma/x1000-dma.h b/include/dt-bindings/dma/x1000-dma.h new file mode 100644 index 000000000000..401e1656e696 --- /dev/null +++ b/include/dt-bindings/dma/x1000-dma.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides macros for X1000 DMA bindings. + * + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com> + */ + +#ifndef __DT_BINDINGS_DMA_X1000_DMA_H__ +#define __DT_BINDINGS_DMA_X1000_DMA_H__ + +/* + * Request type numbers for the X1000 DMA controller (written to the DRTn + * register for the channel). + */ +#define X1000_DMA_DMIC_RX 0x5 +#define X1000_DMA_I2S0_TX 0x6 +#define X1000_DMA_I2S0_RX 0x7 +#define X1000_DMA_AUTO 0x8 +#define X1000_DMA_UART2_TX 0x10 +#define X1000_DMA_UART2_RX 0x11 +#define X1000_DMA_UART1_TX 0x12 +#define X1000_DMA_UART1_RX 0x13 +#define X1000_DMA_UART0_TX 0x14 +#define X1000_DMA_UART0_RX 0x15 +#define X1000_DMA_SSI0_TX 0x16 +#define X1000_DMA_SSI0_RX 0x17 +#define X1000_DMA_MSC0_TX 0x1a +#define X1000_DMA_MSC0_RX 0x1b +#define X1000_DMA_MSC1_TX 0x1c +#define X1000_DMA_MSC1_RX 0x1d +#define X1000_DMA_PCM0_TX 0x20 +#define X1000_DMA_PCM0_RX 0x21 +#define X1000_DMA_SMB0_TX 0x24 +#define X1000_DMA_SMB0_RX 0x25 +#define X1000_DMA_SMB1_TX 0x26 +#define X1000_DMA_SMB1_RX 0x27 +#define X1000_DMA_SMB2_TX 0x28 +#define X1000_DMA_SMB2_RX 0x29 + +#endif /* __DT_BINDINGS_DMA_X1000_DMA_H__ */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h new file mode 100644 index 000000000000..40e57a5ff1db --- /dev/null +++ b/include/dt-bindings/gpio/meson-a1-gpio.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +#define _DT_BINDINGS_MESON_A1_GPIO_H + +#define GPIOP_0 0 +#define GPIOP_1 1 +#define GPIOP_2 2 +#define GPIOP_3 3 +#define GPIOP_4 4 +#define GPIOP_5 5 +#define GPIOP_6 6 +#define GPIOP_7 7 +#define GPIOP_8 8 +#define GPIOP_9 9 +#define GPIOP_10 10 +#define GPIOP_11 11 +#define GPIOP_12 12 +#define GPIOB_0 13 +#define GPIOB_1 14 +#define GPIOB_2 15 +#define GPIOB_3 16 +#define GPIOB_4 17 +#define GPIOB_5 18 +#define GPIOB_6 19 +#define GPIOX_0 20 +#define GPIOX_1 21 +#define GPIOX_2 22 +#define GPIOX_3 23 +#define GPIOX_4 24 +#define GPIOX_5 25 +#define GPIOX_6 26 +#define GPIOX_7 27 +#define GPIOX_8 28 +#define GPIOX_9 29 +#define GPIOX_10 30 +#define GPIOX_11 31 +#define GPIOX_12 32 +#define GPIOX_13 33 +#define GPIOX_14 34 +#define GPIOX_15 35 +#define GPIOX_16 36 +#define GPIOF_0 37 +#define GPIOF_1 38 +#define GPIOF_2 39 +#define GPIOF_3 40 +#define GPIOF_4 41 +#define GPIOF_5 42 +#define GPIOF_6 43 +#define GPIOF_7 44 +#define GPIOF_8 45 +#define GPIOF_9 46 +#define GPIOF_10 47 +#define GPIOF_11 48 +#define GPIOF_12 49 +#define GPIOA_0 50 +#define GPIOA_1 51 +#define GPIOA_2 52 +#define GPIOA_3 53 +#define GPIOA_4 54 +#define GPIOA_5 55 +#define GPIOA_6 56 +#define GPIOA_7 57 +#define GPIOA_8 58 +#define GPIOA_9 59 +#define GPIOA_10 60 +#define GPIOA_11 61 + +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/iio/adc/ingenic,adc.h b/include/dt-bindings/iio/adc/ingenic,adc.h index 82706b2706ac..42f871ab3272 100644 --- a/include/dt-bindings/iio/adc/ingenic,adc.h +++ b/include/dt-bindings/iio/adc/ingenic,adc.h @@ -6,5 +6,6 @@ /* ADC channel idx. */ #define INGENIC_ADC_AUX 0 #define INGENIC_ADC_BATTERY 1 +#define INGENIC_ADC_AUX2 2 #endif diff --git a/include/dt-bindings/interconnect/qcom,msm8974.h b/include/dt-bindings/interconnect/qcom,msm8974.h new file mode 100644 index 000000000000..e65ae27ffff2 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8974.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Qualcomm msm8974 interconnect IDs + * + * Copyright (c) 2019 Brian Masney <masneyb@onstation.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H + +#define BIMC_MAS_AMPSS_M0 0 +#define BIMC_MAS_AMPSS_M1 1 +#define BIMC_MAS_MSS_PROC 2 +#define BIMC_TO_MNOC 3 +#define BIMC_TO_SNOC 4 +#define BIMC_SLV_EBI_CH0 5 +#define BIMC_SLV_AMPSS_L2 6 + +#define CNOC_MAS_RPM_INST 0 +#define CNOC_MAS_RPM_DATA 1 +#define CNOC_MAS_RPM_SYS 2 +#define CNOC_MAS_DEHR 3 +#define CNOC_MAS_QDSS_DAP 4 +#define CNOC_MAS_SPDM 5 +#define CNOC_MAS_TIC 6 +#define CNOC_SLV_CLK_CTL 7 +#define CNOC_SLV_CNOC_MSS 8 +#define CNOC_SLV_SECURITY 9 +#define CNOC_SLV_TCSR 10 +#define CNOC_SLV_TLMM 11 +#define CNOC_SLV_CRYPTO_0_CFG 12 +#define CNOC_SLV_CRYPTO_1_CFG 13 +#define CNOC_SLV_IMEM_CFG 14 +#define CNOC_SLV_MESSAGE_RAM 15 +#define CNOC_SLV_BIMC_CFG 16 +#define CNOC_SLV_BOOT_ROM 17 +#define CNOC_SLV_PMIC_ARB 18 +#define CNOC_SLV_SPDM_WRAPPER 19 +#define CNOC_SLV_DEHR_CFG 20 +#define CNOC_SLV_MPM 21 +#define CNOC_SLV_QDSS_CFG 22 +#define CNOC_SLV_RBCPR_CFG 23 +#define CNOC_SLV_RBCPR_QDSS_APU_CFG 24 +#define CNOC_TO_SNOC 25 +#define CNOC_SLV_CNOC_ONOC_CFG 26 +#define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27 +#define CNOC_SLV_CNOC_MNOC_CFG 28 +#define CNOC_SLV_PNOC_CFG 29 +#define CNOC_SLV_SNOC_MPU_CFG 30 +#define CNOC_SLV_SNOC_CFG 31 +#define CNOC_SLV_EBI1_DLL_CFG 32 +#define CNOC_SLV_PHY_APU_CFG 33 +#define CNOC_SLV_EBI1_PHY_CFG 34 +#define CNOC_SLV_RPM 35 +#define CNOC_SLV_SERVICE_CNOC 36 + +#define MNOC_MAS_GRAPHICS_3D 0 +#define MNOC_MAS_JPEG 1 +#define MNOC_MAS_MDP_PORT0 2 +#define MNOC_MAS_VIDEO_P0 3 +#define MNOC_MAS_VIDEO_P1 4 +#define MNOC_MAS_VFE 5 +#define MNOC_TO_CNOC 6 +#define MNOC_TO_BIMC 7 +#define MNOC_SLV_CAMERA_CFG 8 +#define MNOC_SLV_DISPLAY_CFG 9 +#define MNOC_SLV_OCMEM_CFG 10 +#define MNOC_SLV_CPR_CFG 11 +#define MNOC_SLV_CPR_XPU_CFG 12 +#define MNOC_SLV_MISC_CFG 13 +#define MNOC_SLV_MISC_XPU_CFG 14 +#define MNOC_SLV_VENUS_CFG 15 +#define MNOC_SLV_GRAPHICS_3D_CFG 16 +#define MNOC_SLV_MMSS_CLK_CFG 17 +#define MNOC_SLV_MMSS_CLK_XPU_CFG 18 +#define MNOC_SLV_MNOC_MPU_CFG 19 +#define MNOC_SLV_ONOC_MPU_CFG 20 +#define MNOC_SLV_SERVICE_MNOC 21 + +#define OCMEM_NOC_TO_OCMEM_VNOC 0 +#define OCMEM_MAS_JPEG_OCMEM 1 +#define OCMEM_MAS_MDP_OCMEM 2 +#define OCMEM_MAS_VIDEO_P0_OCMEM 3 +#define OCMEM_MAS_VIDEO_P1_OCMEM 4 +#define OCMEM_MAS_VFE_OCMEM 5 +#define OCMEM_MAS_CNOC_ONOC_CFG 6 +#define OCMEM_SLV_SERVICE_ONOC 7 +#define OCMEM_VNOC_TO_SNOC 8 +#define OCMEM_VNOC_TO_OCMEM_NOC 9 +#define OCMEM_VNOC_MAS_GFX3D 10 +#define OCMEM_SLV_OCMEM 11 + +#define PNOC_MAS_PNOC_CFG 0 +#define PNOC_MAS_SDCC_1 1 +#define PNOC_MAS_SDCC_3 2 +#define PNOC_MAS_SDCC_4 3 +#define PNOC_MAS_SDCC_2 4 +#define PNOC_MAS_TSIF 5 +#define PNOC_MAS_BAM_DMA 6 +#define PNOC_MAS_BLSP_2 7 +#define PNOC_MAS_USB_HSIC 8 +#define PNOC_MAS_BLSP_1 9 +#define PNOC_MAS_USB_HS 10 +#define PNOC_TO_SNOC 11 +#define PNOC_SLV_SDCC_1 12 +#define PNOC_SLV_SDCC_3 13 +#define PNOC_SLV_SDCC_2 14 +#define PNOC_SLV_SDCC_4 15 +#define PNOC_SLV_TSIF 16 +#define PNOC_SLV_BAM_DMA 17 +#define PNOC_SLV_BLSP_2 18 +#define PNOC_SLV_USB_HSIC 19 +#define PNOC_SLV_BLSP_1 20 +#define PNOC_SLV_USB_HS 21 +#define PNOC_SLV_PDM 22 +#define PNOC_SLV_PERIPH_APU_CFG 23 +#define PNOC_SLV_PNOC_MPU_CFG 24 +#define PNOC_SLV_PRNG 25 +#define PNOC_SLV_SERVICE_PNOC 26 + +#define SNOC_MAS_LPASS_AHB 0 +#define SNOC_MAS_QDSS_BAM 1 +#define SNOC_MAS_SNOC_CFG 2 +#define SNOC_TO_BIMC 3 +#define SNOC_TO_CNOC 4 +#define SNOC_TO_PNOC 5 +#define SNOC_TO_OCMEM_VNOC 6 +#define SNOC_MAS_CRYPTO_CORE0 7 +#define SNOC_MAS_CRYPTO_CORE1 8 +#define SNOC_MAS_LPASS_PROC 9 +#define SNOC_MAS_MSS 10 +#define SNOC_MAS_MSS_NAV 11 +#define SNOC_MAS_OCMEM_DMA 12 +#define SNOC_MAS_WCSS 13 +#define SNOC_MAS_QDSS_ETR 14 +#define SNOC_MAS_USB3 15 +#define SNOC_SLV_AMPSS 16 +#define SNOC_SLV_LPASS 17 +#define SNOC_SLV_USB3 18 +#define SNOC_SLV_WCSS 19 +#define SNOC_SLV_OCIMEM 20 +#define SNOC_SLV_SNOC_OCMEM 21 +#define SNOC_SLV_SERVICE_SNOC 22 +#define SNOC_SLV_QDSS_STM 23 + +#endif diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h new file mode 100644 index 000000000000..9c046c7242ed --- /dev/null +++ b/include/dt-bindings/net/qca-ar803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Qualcomm Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_QCA_AR803X_H +#define _DT_BINDINGS_QCA_AR803X_H + +#define AR803X_STRENGTH_FULL 0 +#define AR803X_STRENGTH_HALF 1 +#define AR803X_STRENGTH_QUARTER 2 + +#endif diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h new file mode 100644 index 000000000000..218b1a64e975 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83869.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Texas Instruments DP83869 PHY + * + * Author: Dan Murphy <dmurphy@ti.com> + * + * Copyright: (C) 2019 Texas Instruments, Inc. + */ + +#ifndef _DT_BINDINGS_TI_DP83869_H +#define _DT_BINDINGS_TI_DP83869_H + +/* PHY CTRL bits */ +#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* IO_MUX_CFG - Clock output selection */ +#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa +#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb +#define DP83869_CLK_O_SEL_REF_CLK 0xc + +#define DP83869_RGMII_COPPER_ETHERNET 0x00 +#define DP83869_RGMII_1000_BASE 0x01 +#define DP83869_RGMII_100_BASE 0x02 +#define DP83869_RGMII_SGMII_BRIDGE 0x03 +#define DP83869_1000M_MEDIA_CONVERT 0x04 +#define DP83869_100M_MEDIA_CONVERT 0x05 +#define DP83869_SGMII_COPPER_ETHERNET 0x06 + +#endif diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index 3831f91fb3ba..e8e117306b1b 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -27,8 +27,8 @@ #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) -#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) -#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) +#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) +#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) #define AT91_PIOA 0 #define AT91_PIOB 1 diff --git a/include/dt-bindings/pmu/exynos_ppmu.h b/include/dt-bindings/pmu/exynos_ppmu.h new file mode 100644 index 000000000000..8724abe130f3 --- /dev/null +++ b/include/dt-bindings/pmu/exynos_ppmu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos PPMU event types for counting in regs + * + * Copyright (c) 2019, Samsung Electronics + * Author: Lukasz Luba <l.luba@partner.samsung.com> + */ + +#ifndef __DT_BINDINGS_PMU_EXYNOS_PPMU_H +#define __DT_BINDINGS_PMU_EXYNOS_PPMU_H + +#define PPMU_RO_BUSY_CYCLE_CNT 0x0 +#define PPMU_WO_BUSY_CYCLE_CNT 0x1 +#define PPMU_RW_BUSY_CYCLE_CNT 0x2 +#define PPMU_RO_REQUEST_CNT 0x3 +#define PPMU_WO_REQUEST_CNT 0x4 +#define PPMU_RO_DATA_CNT 0x5 +#define PPMU_WO_DATA_CNT 0x6 +#define PPMU_RO_LATENCY 0x12 +#define PPMU_WO_LATENCY 0x16 +#define PPMU_V2_RO_DATA_CNT 0x4 +#define PPMU_V2_WO_DATA_CNT 0x5 +#define PPMU_V2_EVT3_RW_DATA_CNT 0x22 + +#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 93e36d011527..f05f8b1808ec 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -27,6 +27,14 @@ #define RPMH_REGULATOR_LEVEL_TURBO 384 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +/* MSM8976 Power Domain Indexes */ +#define MSM8976_VDDCX 0 +#define MSM8976_VDDCX_AO 1 +#define MSM8976_VDDCX_VFL 2 +#define MSM8976_VDDMX 3 +#define MSM8976_VDDMX_AO 4 +#define MSM8976_VDDMX_VFL 5 + /* MSM8996 Power Domain Indexes */ #define MSM8996_VDDCX 0 #define MSM8996_VDDCX_AO 1 @@ -68,6 +76,7 @@ #define RPM_SMD_LEVEL_NOM_PLUS 320 #define RPM_SMD_LEVEL_TURBO 384 #define RPM_SMD_LEVEL_TURBO_NO_CPR 416 +#define RPM_SMD_LEVEL_TURBO_HIGH 448 #define RPM_SMD_LEVEL_BINNING 512 #endif diff --git a/include/dt-bindings/regulator/dlg,da9063-regulator.h b/include/dt-bindings/regulator/dlg,da9063-regulator.h new file mode 100644 index 000000000000..1de710dd0899 --- /dev/null +++ b/include/dt-bindings/regulator/dlg,da9063-regulator.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H +#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H + +/* + * These buck mode constants may be used to specify values in device tree + * properties (e.g. regulator-initial-mode). + * A description of the following modes is in the manufacturers datasheet. + */ + +#define DA9063_BUCK_MODE_SLEEP 1 +#define DA9063_BUCK_MODE_SYNC 2 +#define DA9063_BUCK_MODE_AUTO 3 + +#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index 000000000000..f1a3a797540d --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_AM2AXI_VAD 1 +/* 2-3 */ +#define RESET_PSRAM 4 +#define RESET_PAD_CTRL 5 +/* 6 */ +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +/* 9 */ +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO 12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD 15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +/* 20 */ +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +/* 23 */ +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 +/* 30-31 */ + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A 34 +/* 35 */ +#define RESET_USBCTRL 36 +/* 37 */ +#define RESET_USBPHY 38 +/* 39-41 */ +#define RESET_RSA 42 +#define RESET_DMC 43 +/* 44 */ +#define RESET_IRQ_CTRL 45 +/* 46 */ +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +/* 51-52 */ +#define RESET_ROM 53 +#define RESET_SPIFC 54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 +/* 60-63 */ + +/* RESET2 */ +/* 64-95 */ + +#endif diff --git a/include/dt-bindings/sound/samsung-i2s.h b/include/dt-bindings/sound/samsung-i2s.h index 77545f14c379..250de0d6c734 100644 --- a/include/dt-bindings/sound/samsung-i2s.h +++ b/include/dt-bindings/sound/samsung-i2s.h @@ -2,8 +2,14 @@ #ifndef _DT_BINDINGS_SAMSUNG_I2S_H #define _DT_BINDINGS_SAMSUNG_I2S_H -#define CLK_I2S_CDCLK 0 -#define CLK_I2S_RCLK_SRC 1 -#define CLK_I2S_RCLK_PSR 2 +#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ + +#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to + * RCLKSRC bit in IISMOD register) + */ + +#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock + * (corresponding to the IISPSR register) + */ #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ |