diff options
Diffstat (limited to 'include/dt-bindings')
47 files changed, 724 insertions, 34 deletions
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index bcbe9ee2cdaf..be12e1dd1f38 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -215,6 +215,7 @@ #define QCOM_ID_SDA429W 437 #define QCOM_ID_SM8350 439 #define QCOM_ID_QCM2290 441 +#define QCOM_ID_SM7125 443 #define QCOM_ID_SM6115 444 #define QCOM_ID_IPQ5010 446 #define QCOM_ID_IPQ5018 447 @@ -249,8 +250,8 @@ #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 +#define QCOM_ID_SM4450 568 #define QCOM_ID_QDU1010 587 -#define QCOM_ID_IPQ5019 569 #define QCOM_ID_QRU1032 588 #define QCOM_ID_QRU1052 589 #define QCOM_ID_QRU1062 590 diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h index 77997b35612c..b3f3b7cf9af8 100644 --- a/include/dt-bindings/ata/ahci.h +++ b/include/dt-bindings/ata/ahci.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* * This header provides constants for most AHCI bindings. */ diff --git a/include/dt-bindings/clock/hi3559av100-clock.h b/include/dt-bindings/clock/hi3559av100-clock.h index 5fe7689010a0..a4f0e997546c 100644 --- a/include/dt-bindings/clock/hi3559av100-clock.h +++ b/include/dt-bindings/clock/hi3559av100-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */ /* * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. * diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-bindings/clock/intel,agilex5-clkmgr.h new file mode 100644 index 000000000000..2f3a23b31c5c --- /dev/null +++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023, Intel Corporation + */ + +#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H +#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_F2S_FREE_CLK 3 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 4 +#define AGILEX5_MAIN_PLL_C0_CLK 5 +#define AGILEX5_MAIN_PLL_C1_CLK 6 +#define AGILEX5_MAIN_PLL_C2_CLK 7 +#define AGILEX5_MAIN_PLL_C3_CLK 8 +#define AGILEX5_PERIPH_PLL_CLK 9 +#define AGILEX5_PERIPH_PLL_C0_CLK 10 +#define AGILEX5_PERIPH_PLL_C1_CLK 11 +#define AGILEX5_PERIPH_PLL_C2_CLK 12 +#define AGILEX5_PERIPH_PLL_C3_CLK 13 +#define AGILEX5_CORE0_FREE_CLK 14 +#define AGILEX5_CORE1_FREE_CLK 15 +#define AGILEX5_CORE2_FREE_CLK 16 +#define AGILEX5_CORE3_FREE_CLK 17 +#define AGILEX5_DSU_FREE_CLK 18 +#define AGILEX5_BOOT_CLK 19 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 20 +#define AGILEX5_NOC_FREE_CLK 21 +#define AGILEX5_S2F_USR0_CLK 22 +#define AGILEX5_NOC_CLK 23 +#define AGILEX5_EMAC_A_FREE_CLK 24 +#define AGILEX5_EMAC_B_FREE_CLK 25 +#define AGILEX5_EMAC_PTP_FREE_CLK 26 +#define AGILEX5_GPIO_DB_FREE_CLK 27 +#define AGILEX5_S2F_USER0_FREE_CLK 28 +#define AGILEX5_S2F_USER1_FREE_CLK 29 +#define AGILEX5_PSI_REF_FREE_CLK 30 +#define AGILEX5_USB31_FREE_CLK 31 + +/* Gate clocks */ +#define AGILEX5_CORE0_CLK 32 +#define AGILEX5_CORE1_CLK 33 +#define AGILEX5_CORE2_CLK 34 +#define AGILEX5_CORE3_CLK 35 +#define AGILEX5_MPU_CLK 36 +#define AGILEX5_MPU_PERIPH_CLK 37 +#define AGILEX5_MPU_CCU_CLK 38 +#define AGILEX5_L4_MAIN_CLK 39 +#define AGILEX5_L4_MP_CLK 40 +#define AGILEX5_L4_SYS_FREE_CLK 41 +#define AGILEX5_L4_SP_CLK 42 +#define AGILEX5_CS_AT_CLK 43 +#define AGILEX5_CS_TRACE_CLK 44 +#define AGILEX5_CS_PDBG_CLK 45 +#define AGILEX5_EMAC1_CLK 47 +#define AGILEX5_EMAC2_CLK 48 +#define AGILEX5_EMAC_PTP_CLK 49 +#define AGILEX5_GPIO_DB_CLK 50 +#define AGILEX5_S2F_USER0_CLK 51 +#define AGILEX5_S2F_USER1_CLK 52 +#define AGILEX5_PSI_REF_CLK 53 +#define AGILEX5_USB31_SUSPEND_CLK 54 +#define AGILEX5_EMAC0_CLK 46 +#define AGILEX5_USB31_BUS_CLK_EARLY 55 +#define AGILEX5_USB2OTG_HCLK 56 +#define AGILEX5_SPIM_0_CLK 57 +#define AGILEX5_SPIM_1_CLK 58 +#define AGILEX5_SPIS_0_CLK 59 +#define AGILEX5_SPIS_1_CLK 60 +#define AGILEX5_DMA_CORE_CLK 61 +#define AGILEX5_DMA_HS_CLK 62 +#define AGILEX5_I3C_0_CORE_CLK 63 +#define AGILEX5_I3C_1_CORE_CLK 64 +#define AGILEX5_I2C_0_PCLK 65 +#define AGILEX5_I2C_1_PCLK 66 +#define AGILEX5_I2C_EMAC0_PCLK 67 +#define AGILEX5_I2C_EMAC1_PCLK 68 +#define AGILEX5_I2C_EMAC2_PCLK 69 +#define AGILEX5_UART_0_PCLK 70 +#define AGILEX5_UART_1_PCLK 71 +#define AGILEX5_SPTIMER_0_PCLK 72 +#define AGILEX5_SPTIMER_1_PCLK 73 +#define AGILEX5_DFI_CLK 74 +#define AGILEX5_NAND_NF_CLK 75 +#define AGILEX5_NAND_BCH_CLK 76 +#define AGILEX5_SDMMC_SDPHY_REG_CLK 77 +#define AGILEX5_SDMCLK 78 +#define AGILEX5_SOFTPHY_REG_PCLK 79 +#define AGILEX5_SOFTPHY_PHY_CLK 80 +#define AGILEX5_SOFTPHY_CTRL_CLK 81 +#define AGILEX5_NUM_CLKS 82 + +#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..f3de2fdfeea1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define UBI32_PLL_MAIN 6 +#define UBI32_PLL 7 +#define ADSS_PWM_CLK_SRC 8 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 +#define BLSP1_UART1_APPS_CLK_SRC 15 +#define BLSP1_UART2_APPS_CLK_SRC 16 +#define CRYPTO_CLK_SRC 17 +#define GCC_ADSS_PWM_CLK 18 +#define GCC_BLSP1_AHB_CLK 19 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_BTSS_LPO_CLK 28 +#define GCC_CMN_BLK_AHB_CLK 29 +#define GCC_CMN_BLK_SYS_CLK 30 +#define GCC_CRYPTO_AHB_CLK 31 +#define GCC_CRYPTO_AXI_CLK 32 +#define GCC_CRYPTO_CLK 33 +#define GCC_CRYPTO_PPE_CLK 34 +#define GCC_DCC_CLK 35 +#define GCC_GEPHY_RX_CLK 36 +#define GCC_GEPHY_TX_CLK 37 +#define GCC_GMAC0_CFG_CLK 38 +#define GCC_GMAC0_PTP_CLK 39 +#define GCC_GMAC0_RX_CLK 40 +#define GCC_GMAC0_SYS_CLK 41 +#define GCC_GMAC0_TX_CLK 42 +#define GCC_GMAC1_CFG_CLK 43 +#define GCC_GMAC1_PTP_CLK 44 +#define GCC_GMAC1_RX_CLK 45 +#define GCC_GMAC1_SYS_CLK 46 +#define GCC_GMAC1_TX_CLK 47 +#define GCC_GP1_CLK 48 +#define GCC_GP2_CLK 49 +#define GCC_GP3_CLK 50 +#define GCC_LPASS_CORE_AXIM_CLK 51 +#define GCC_LPASS_SWAY_CLK 52 +#define GCC_MDIO0_AHB_CLK 53 +#define GCC_MDIO1_AHB_CLK 54 +#define GCC_PCIE0_AHB_CLK 55 +#define GCC_PCIE0_AUX_CLK 56 +#define GCC_PCIE0_AXI_M_CLK 57 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58 +#define GCC_PCIE0_AXI_S_CLK 59 +#define GCC_PCIE0_PIPE_CLK 60 +#define GCC_PCIE1_AHB_CLK 61 +#define GCC_PCIE1_AUX_CLK 62 +#define GCC_PCIE1_AXI_M_CLK 63 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64 +#define GCC_PCIE1_AXI_S_CLK 65 +#define GCC_PCIE1_PIPE_CLK 66 +#define GCC_PRNG_AHB_CLK 67 +#define GCC_Q6_AXIM_CLK 68 +#define GCC_Q6_AXIM2_CLK 69 +#define GCC_Q6_AXIS_CLK 70 +#define GCC_Q6_AHB_CLK 71 +#define GCC_Q6_AHB_S_CLK 72 +#define GCC_Q6_TSCTR_1TO2_CLK 73 +#define GCC_Q6SS_ATBM_CLK 74 +#define GCC_Q6SS_PCLKDBG_CLK 75 +#define GCC_Q6SS_TRIG_CLK 76 +#define GCC_QDSS_AT_CLK 77 +#define GCC_QDSS_CFG_AHB_CLK 78 +#define GCC_QDSS_DAP_AHB_CLK 79 +#define GCC_QDSS_DAP_CLK 80 +#define GCC_QDSS_ETR_USB_CLK 81 +#define GCC_QDSS_EUD_AT_CLK 82 +#define GCC_QDSS_STM_CLK 83 +#define GCC_QDSS_TRACECLKIN_CLK 84 +#define GCC_QDSS_TSCTR_DIV8_CLK 85 +#define GCC_QPIC_AHB_CLK 86 +#define GCC_QPIC_CLK 87 +#define GCC_QPIC_IO_MACRO_CLK 88 +#define GCC_SDCC1_AHB_CLK 89 +#define GCC_SDCC1_APPS_CLK 90 +#define GCC_SLEEP_CLK_SRC 91 +#define GCC_SNOC_GMAC0_AHB_CLK 92 +#define GCC_SNOC_GMAC0_AXI_CLK 93 +#define GCC_SNOC_GMAC1_AHB_CLK 94 +#define GCC_SNOC_GMAC1_AXI_CLK 95 +#define GCC_SNOC_LPASS_AXIM_CLK 96 +#define GCC_SNOC_LPASS_SWAY_CLK 97 +#define GCC_SNOC_UBI0_AXI_CLK 98 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 99 +#define GCC_SYS_NOC_PCIE1_AXI_CLK 100 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 +#define GCC_SYS_NOC_USB0_AXI_CLK 102 +#define GCC_SYS_NOC_WCSS_AHB_CLK 103 +#define GCC_UBI0_AXI_CLK 104 +#define GCC_UBI0_CFG_CLK 105 +#define GCC_UBI0_CORE_CLK 106 +#define GCC_UBI0_DBG_CLK 107 +#define GCC_UBI0_NC_AXI_CLK 108 +#define GCC_UBI0_UTCM_CLK 109 +#define GCC_UNIPHY_AHB_CLK 110 +#define GCC_UNIPHY_RX_CLK 111 +#define GCC_UNIPHY_SYS_CLK 112 +#define GCC_UNIPHY_TX_CLK 113 +#define GCC_USB0_AUX_CLK 114 +#define GCC_USB0_EUD_AT_CLK 115 +#define GCC_USB0_LFPS_CLK 116 +#define GCC_USB0_MASTER_CLK 117 +#define GCC_USB0_MOCK_UTMI_CLK 118 +#define GCC_USB0_PHY_CFG_AHB_CLK 119 +#define GCC_USB0_SLEEP_CLK 120 +#define GCC_WCSS_ACMT_CLK 121 +#define GCC_WCSS_AHB_S_CLK 122 +#define GCC_WCSS_AXI_M_CLK 123 +#define GCC_WCSS_AXI_S_CLK 124 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 +#define GCC_WCSS_DBG_IFC_APB_CLK 126 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 +#define GCC_WCSS_DBG_IFC_ATB_CLK 128 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 +#define GCC_WCSS_DBG_IFC_NTS_CLK 132 +#define GCC_WCSS_ECAHB_CLK 133 +#define GCC_XO_CLK 134 +#define GCC_XO_CLK_SRC 135 +#define GMAC0_RX_CLK_SRC 136 +#define GMAC0_TX_CLK_SRC 137 +#define GMAC1_RX_CLK_SRC 138 +#define GMAC1_TX_CLK_SRC 139 +#define GMAC_CLK_SRC 140 +#define GP1_CLK_SRC 141 +#define GP2_CLK_SRC 142 +#define GP3_CLK_SRC 143 +#define LPASS_AXIM_CLK_SRC 144 +#define LPASS_SWAY_CLK_SRC 145 +#define PCIE0_AUX_CLK_SRC 146 +#define PCIE0_AXI_CLK_SRC 147 +#define PCIE1_AUX_CLK_SRC 148 +#define PCIE1_AXI_CLK_SRC 149 +#define PCNOC_BFDCD_CLK_SRC 150 +#define Q6_AXI_CLK_SRC 151 +#define QDSS_AT_CLK_SRC 152 +#define QDSS_STM_CLK_SRC 153 +#define QDSS_TSCTR_CLK_SRC 154 +#define QDSS_TRACECLKIN_CLK_SRC 155 +#define QPIC_IO_MACRO_CLK_SRC 156 +#define SDCC1_APPS_CLK_SRC 157 +#define SYSTEM_NOC_BFDCD_CLK_SRC 158 +#define UBI0_AXI_CLK_SRC 159 +#define UBI0_CORE_CLK_SRC 160 +#define USB0_AUX_CLK_SRC 161 +#define USB0_LFPS_CLK_SRC 162 +#define USB0_MASTER_CLK_SRC 163 +#define USB0_MOCK_UTMI_CLK_SRC 164 +#define WCSS_AHB_CLK_SRC 165 +#define PCIE0_PIPE_CLK_SRC 166 +#define PCIE1_PIPE_CLK_SRC 167 +#define USB0_PIPE_CLK_SRC 168 +#define GCC_USB0_PIPE_CLK 169 +#define GMAC0_RX_DIV_CLK_SRC 170 +#define GMAC0_TX_DIV_CLK_SRC 171 +#define GMAC1_RX_DIV_CLK_SRC 172 +#define GMAC1_TX_DIV_CLK_SRC 173 +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58f..b5456a64d421 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h index 721105ea4fad..845491591784 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -494,5 +494,15 @@ #define USB30_SEC_GDSC 11 #define EMAC_0_GDSC 12 #define EMAC_1_GDSC 13 +#define USB4_1_GDSC 14 +#define USB4_GDSC 15 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21 +#define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22 +#define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index b32a7aa65349..08fd3a37acaa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -214,4 +214,6 @@ #define GCC_CRYPTO_CLK 205 #define GCC_CRYPTO_AXI_CLK 206 #define GCC_CRYPTO_AHB_CLK 207 +#define GCC_USB0_PIPE_CLK 208 +#define GCC_USB0_SLEEP_CLK 209 #endif diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h index f2ae1c6a82dd..c34be5624954 100644 --- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index b5616bca7b44..5790b1391201 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (c) 2021 Rockchip Electronics Co. Ltd. * Copyright (c) 2022 Collabora Ltd. diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..467ccab3bfaa 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -1,11 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1 @@ -218,4 +225,77 @@ #define JH7110_AONCLK_END 14 +/* STGCRG clocks */ +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 +#define JH7110_STGCLK_USB0_APB 1 +#define JH7110_STGCLK_USB0_UTMI_APB 2 +#define JH7110_STGCLK_USB0_AXI 3 +#define JH7110_STGCLK_USB0_LPM 4 +#define JH7110_STGCLK_USB0_STB 5 +#define JH7110_STGCLK_USB0_APP_125 6 +#define JH7110_STGCLK_USB0_REFCLK 7 +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 +#define JH7110_STGCLK_PCIE0_APB 9 +#define JH7110_STGCLK_PCIE0_TL 10 +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 +#define JH7110_STGCLK_PCIE1_APB 12 +#define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 +#define JH7110_STGCLK_GRP0_MAIN 17 +#define JH7110_STGCLK_GRP0_BUS 18 +#define JH7110_STGCLK_GRP0_STG 19 +#define JH7110_STGCLK_GRP1_MAIN 20 +#define JH7110_STGCLK_GRP1_BUS 21 +#define JH7110_STGCLK_GRP1_STG 22 +#define JH7110_STGCLK_GRP1_HIFI 23 +#define JH7110_STGCLK_E2_RTC 24 +#define JH7110_STGCLK_E2_CORE 25 +#define JH7110_STGCLK_E2_DBG 26 +#define JH7110_STGCLK_DMA1P_AXI 27 +#define JH7110_STGCLK_DMA1P_AHB 28 + +#define JH7110_STGCLK_END 29 + +/* ISPCRG clocks */ +#define JH7110_ISPCLK_DOM4_APB_FUNC 0 +#define JH7110_ISPCLK_MIPI_RX0_PXL 1 +#define JH7110_ISPCLK_DVP_INV 2 +#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 +#define JH7110_ISPCLK_M31DPHY_REF_IN 4 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 +#define JH7110_ISPCLK_VIN_APB 6 +#define JH7110_ISPCLK_VIN_SYS 7 +#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 +#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 +#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 +#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 +#define JH7110_ISPCLK_VIN_P_AXI_WR 12 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 + +#define JH7110_ISPCLK_END 14 + +/* VOUTCRG clocks */ +#define JH7110_VOUTCLK_APB 0 +#define JH7110_VOUTCLK_DC8200_PIX 1 +#define JH7110_VOUTCLK_DSI_SYS 2 +#define JH7110_VOUTCLK_TX_ESC 3 +#define JH7110_VOUTCLK_DC8200_AXI 4 +#define JH7110_VOUTCLK_DC8200_CORE 5 +#define JH7110_VOUTCLK_DC8200_AHB 6 +#define JH7110_VOUTCLK_DC8200_PIX0 7 +#define JH7110_VOUTCLK_DC8200_PIX1 8 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 +#define JH7110_VOUTCLK_DSITX_APB 10 +#define JH7110_VOUTCLK_DSITX_SYS 11 +#define JH7110_VOUTCLK_DSITX_DPI 12 +#define JH7110_VOUTCLK_DSITX_TXESC 13 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 +#define JH7110_VOUTCLK_HDMI_TX_SYS 17 + +#define JH7110_VOUTCLK_END 18 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 25e8cfd43459..0a5324bcdbda 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h index e143b9929763..fdbfb404f92a 100644 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 huangzhenwei@allwinnertech.com * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h index 4c2697fd32b0..f95c170711e5 100644 --- a/include/dt-bindings/clock/sun20i-d1-r-ccu.h +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> */ diff --git a/include/dt-bindings/clock/sun50i-a100-ccu.h b/include/dt-bindings/clock/sun50i-a100-ccu.h index 28dc36e1a232..06a2031d466b 100644 --- a/include/dt-bindings/clock/sun50i-a100-ccu.h +++ b/include/dt-bindings/clock/sun50i-a100-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h index a1545cd60e75..ef9123d81937 100644 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 1191aca53ac6..6f8f01e67628 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h index c845493e4d37..3bd3aa3d57ce 100644 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ #define _DT_BINDINGS_CLK_SUN6I_RTC_H_ diff --git a/include/dt-bindings/display/sdtv-standards.h b/include/dt-bindings/display/sdtv-standards.h index fbc1a3db2ea7..8249a2b47b79 100644 --- a/include/dt-bindings/display/sdtv-standards.h +++ b/include/dt-bindings/display/sdtv-standards.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only or X11 */ +/* SPDX-License-Identifier: GPL-2.0-only OR X11 */ /* * Copyright 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de> */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index d1dc09e72923..6de8b08e1e79 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -2,17 +2,38 @@ /* * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H #define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H +#define QCOM_SCM_VMID_TZ 0x1 #define QCOM_SCM_VMID_HLOS 0x3 #define QCOM_SCM_VMID_SSC_Q6 0x5 #define QCOM_SCM_VMID_ADSP_Q6 0x6 +#define QCOM_SCM_VMID_CP_TOUCH 0x8 +#define QCOM_SCM_VMID_CP_BITSTREAM 0x9 +#define QCOM_SCM_VMID_CP_PIXEL 0xA +#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB +#define QCOM_SCM_VMID_CP_CAMERA 0xD +#define QCOM_SCM_VMID_HLOS_FREE 0xE #define QCOM_SCM_VMID_MSS_MSA 0xF +#define QCOM_SCM_VMID_MSS_NONMSA 0x10 +#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11 +#define QCOM_SCM_VMID_CP_APP 0x12 +#define QCOM_SCM_VMID_LPASS 0x16 #define QCOM_SCM_VMID_WLAN 0x18 #define QCOM_SCM_VMID_WLAN_CE 0x19 +#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A +#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D +#define QCOM_SCM_VMID_CDSP 0x1E +#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22 +#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24 +#define QCOM_SCM_VMID_ADSP_HEAP 0x25 +#define QCOM_SCM_VMID_CP_CDSP 0x2A #define QCOM_SCM_VMID_NAV 0x2B +#define QCOM_SCM_VMID_TVM 0x2D +#define QCOM_SCM_VMID_OEMVM 0x31 #endif diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h index f7bd69350d18..fa7bb0bbf010 100644 --- a/include/dt-bindings/gpio/meson-g12a-gpio.h +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2018 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen <xingyu.chen@amlogic.com> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 669ca2d6abce..b0b1091aad6d 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -6,6 +6,14 @@ #ifndef _DT_BINDINGS_MUX_TI_SERDES #define _DT_BINDINGS_MUX_TI_SERDES +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure constants values used only + * in DTS board files. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." + /* J721E */ #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 diff --git a/include/dt-bindings/power/amlogic,c3-pwrc.h b/include/dt-bindings/power/amlogic,c3-pwrc.h new file mode 100644 index 000000000000..1d98a25b08a4 --- /dev/null +++ b/include/dt-bindings/power/amlogic,c3-pwrc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. + * Author: hongyu chen1 <hongyu.chen1@amlogic.com> + */ +#ifndef _DT_BINDINGS_AMLOGIC_C3_POWER_H +#define _DT_BINDINGS_AMLOGIC_C3_POWER_H + +#define PWRC_C3_NNA_ID 0 +#define PWRC_C3_AUDIO_ID 1 +#define PWRC_C3_RESV_SEC_ID 2 +#define PWRC_C3_SDIOA_ID 3 +#define PWRC_C3_EMMC_ID 4 +#define PWRC_C3_USB_COMB_ID 5 +#define PWRC_C3_SDCARD_ID 6 +#define PWRC_C3_ETH_ID 7 +#define PWRC_C3_RESV0_ID 8 +#define PWRC_C3_GE2D_ID 9 +#define PWRC_C3_CVE_ID 10 +#define PWRC_C3_GDC_WRAP_ID 11 +#define PWRC_C3_ISP_TOP_ID 12 +#define PWRC_C3_MIPI_ISP_WRAP_ID 13 +#define PWRC_C3_VCODEC_ID 14 + +#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h index 6cf50bfb8ccf..724c370d6853 100644 --- a/include/dt-bindings/power/meson-a1-power.h +++ b/include/dt-bindings/power/meson-a1-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 Amlogic, Inc. * Author: Jianxin Pan <jianxin.pan@amlogic.com> diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h index e5243884b249..ace0e468ce21 100644 --- a/include/dt-bindings/power/meson-axg-power.h +++ b/include/dt-bindings/power/meson-axg-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2020 BayLibre, SAS * Author: Neil Armstrong <narmstrong@baylibre.com> diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h index 93b03bdd60b7..44ec0c50e340 100644 --- a/include/dt-bindings/power/meson-g12a-power.h +++ b/include/dt-bindings/power/meson-g12a-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 BayLibre, SAS * Author: Neil Armstrong <narmstrong@baylibre.com> diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h index 1262dac696c0..8d0b32b6c02c 100644 --- a/include/dt-bindings/power/meson-gxbb-power.h +++ b/include/dt-bindings/power/meson-gxbb-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 BayLibre, SAS * Author: Neil Armstrong <narmstrong@baylibre.com> diff --git a/include/dt-bindings/power/meson-s4-power.h b/include/dt-bindings/power/meson-s4-power.h index 462dd2cb938b..f210a524a592 100644 --- a/include/dt-bindings/power/meson-s4-power.h +++ b/include/dt-bindings/power/meson-s4-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2021 Amlogic, Inc. * Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com> diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h index a020ab00c134..d78e710dbfff 100644 --- a/include/dt-bindings/power/meson-sm1-power.h +++ b/include/dt-bindings/power/meson-sm1-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 BayLibre, SAS * Author: Neil Armstrong <narmstrong@baylibre.com> diff --git a/include/dt-bindings/power/meson8-power.h b/include/dt-bindings/power/meson8-power.h index dd8b2ddb82a7..7a55ba2cd22e 100644 --- a/include/dt-bindings/power/meson8-power.h +++ b/include/dt-bindings/power/meson8-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com> */ diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h new file mode 100644 index 000000000000..7c201a66bc69 --- /dev/null +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_POWER_QCOM_RPMHPD_H +#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H + +/* Generic RPMH Power Domain Indexes */ +#define RPMHPD_CX 0 +#define RPMHPD_CX_AO 1 +#define RPMHPD_EBI 2 +#define RPMHPD_GFX 3 +#define RPMHPD_LCX 4 +#define RPMHPD_LMX 5 +#define RPMHPD_MMCX 6 +#define RPMHPD_MMCX_AO 7 +#define RPMHPD_MX 8 +#define RPMHPD_MX_AO 9 +#define RPMHPD_MXC 10 +#define RPMHPD_MXC_AO 11 +#define RPMHPD_MSS 12 +#define RPMHPD_NSP 13 +#define RPMHPD_NSP0 14 +#define RPMHPD_NSP1 15 +#define RPMHPD_QPHY 16 +#define RPMHPD_DDR 17 +#define RPMHPD_XO 18 + +#endif diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h index 0ec8ad727ed9..cde1536e9ed0 100644 --- a/include/dt-bindings/power/r8a779f0-sysc.h +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h index 1b92fec013cb..6b91a50cc6d6 100644 --- a/include/dt-bindings/power/rk3588-power.h +++ b/include/dt-bindings/power/rk3588-power.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ #define __DT_BINDINGS_POWER_RK3588_POWER_H__ diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h index 3205699b5e41..14f2f9cf2020 100644 --- a/include/dt-bindings/power/summit,smb347-charger.h +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ /* * Author: David Heidelberg <david@ixit.cz> */ diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h new file mode 100644 index 000000000000..b3a974dfc585 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp13-regulator.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 +#define VOLTD_SCMI_SDMMC1_IO 3 +#define VOLTD_SCMI_SDMMC2_IO 4 +#define VOLTD_SCMI_VREFBUF 5 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 6 +#define VOLTD_SCMI_STPMIC1_BUCK2 7 +#define VOLTD_SCMI_STPMIC1_BUCK3 8 +#define VOLTD_SCMI_STPMIC1_BUCK4 9 +#define VOLTD_SCMI_STPMIC1_LDO1 10 +#define VOLTD_SCMI_STPMIC1_LDO2 11 +#define VOLTD_SCMI_STPMIC1_LDO3 12 +#define VOLTD_SCMI_STPMIC1_LDO4 13 +#define VOLTD_SCMI_STPMIC1_LDO5 14 +#define VOLTD_SCMI_STPMIC1_LDO6 15 +#define VOLTD_SCMI_STPMIC1_VREFDDR 16 +#define VOLTD_SCMI_STPMIC1_BOOST 17 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 20 +#define VOLTD_SCMI_REGU1 21 +#define VOLTD_SCMI_REGU2 22 +#define VOLTD_SCMI_REGU3 23 +#define VOLTD_SCMI_REGU4 24 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h index 70ea3a09dbe1..04c4d0c6fd34 100644 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -63,12 +63,15 @@ #define I2C2_RESET 74 #define I2C3_RESET 75 #define I2C4_RESET 76 -/* 77-79 is empty */ +#define I3C0_RESET 77 +#define I3C1_RESET 78 +/* 79 is empty */ #define UART0_RESET 80 #define UART1_RESET 81 /* 82-87 is empty */ #define GPIO0_RESET 88 #define GPIO1_RESET 89 +#define WATCHDOG4_RESET 90 /* BRGMODRST */ #define SOC2FPGA_RESET 96 diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..8f03c92fc23b --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H +#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H + +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0 +#define GCC_BLSP1_BCR 1 +#define GCC_BLSP1_QUP1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_QUP3_BCR 4 +#define GCC_BLSP1_UART1_BCR 5 +#define GCC_BLSP1_UART2_BCR 6 +#define GCC_BOOT_ROM_BCR 7 +#define GCC_BTSS_BCR 8 +#define GCC_CMN_BLK_BCR 9 +#define GCC_CMN_LDO_BCR 10 +#define GCC_CE_BCR 11 +#define GCC_CRYPTO_BCR 12 +#define GCC_DCC_BCR 13 +#define GCC_DCD_BCR 14 +#define GCC_DDRSS_BCR 15 +#define GCC_EDPD_BCR 16 +#define GCC_GEPHY_BCR 17 +#define GCC_GEPHY_MDC_SW_ARES 18 +#define GCC_GEPHY_DSP_HW_ARES 19 +#define GCC_GEPHY_RX_ARES 20 +#define GCC_GEPHY_TX_ARES 21 +#define GCC_GMAC0_BCR 22 +#define GCC_GMAC0_CFG_ARES 23 +#define GCC_GMAC0_SYS_ARES 24 +#define GCC_GMAC1_BCR 25 +#define GCC_GMAC1_CFG_ARES 26 +#define GCC_GMAC1_SYS_ARES 27 +#define GCC_IMEM_BCR 28 +#define GCC_LPASS_BCR 29 +#define GCC_MDIO0_BCR 30 +#define GCC_MDIO1_BCR 31 +#define GCC_MPM_BCR 32 +#define GCC_PCIE0_BCR 33 +#define GCC_PCIE0_LINK_DOWN_BCR 34 +#define GCC_PCIE0_PHY_BCR 35 +#define GCC_PCIE0PHY_PHY_BCR 36 +#define GCC_PCIE0_PIPE_ARES 37 +#define GCC_PCIE0_SLEEP_ARES 38 +#define GCC_PCIE0_CORE_STICKY_ARES 39 +#define GCC_PCIE0_AXI_MASTER_ARES 40 +#define GCC_PCIE0_AXI_SLAVE_ARES 41 +#define GCC_PCIE0_AHB_ARES 42 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44 +#define GCC_PCIE1_BCR 45 +#define GCC_PCIE1_LINK_DOWN_BCR 46 +#define GCC_PCIE1_PHY_BCR 47 +#define GCC_PCIE1PHY_PHY_BCR 48 +#define GCC_PCIE1_PIPE_ARES 49 +#define GCC_PCIE1_SLEEP_ARES 50 +#define GCC_PCIE1_CORE_STICKY_ARES 51 +#define GCC_PCIE1_AXI_MASTER_ARES 52 +#define GCC_PCIE1_AXI_SLAVE_ARES 53 +#define GCC_PCIE1_AHB_ARES 54 +#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55 +#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56 +#define GCC_PCNOC_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68 +#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69 +#define GCC_PRNG_BCR 70 +#define GCC_Q6SS_DBG_ARES 71 +#define GCC_Q6_AHB_S_ARES 72 +#define GCC_Q6_AHB_ARES 73 +#define GCC_Q6_AXIM2_ARES 74 +#define GCC_Q6_AXIM_ARES 75 +#define GCC_Q6_AXIS_ARES 76 +#define GCC_QDSS_BCR 77 +#define GCC_QPIC_BCR 78 +#define GCC_QUSB2_0_PHY_BCR 79 +#define GCC_SDCC1_BCR 80 +#define GCC_SEC_CTRL_BCR 81 +#define GCC_SPDM_BCR 82 +#define GCC_SYSTEM_NOC_BCR 83 +#define GCC_TCSR_BCR 84 +#define GCC_TLMM_BCR 85 +#define GCC_UBI0_AXI_ARES 86 +#define GCC_UBI0_AHB_ARES 87 +#define GCC_UBI0_NC_AXI_ARES 88 +#define GCC_UBI0_DBG_ARES 89 +#define GCC_UBI0_UTCM_ARES 90 +#define GCC_UBI0_CORE_ARES 91 +#define GCC_UBI32_BCR 92 +#define GCC_UNIPHY_BCR 93 +#define GCC_UNIPHY_AHB_ARES 94 +#define GCC_UNIPHY_SYS_ARES 95 +#define GCC_UNIPHY_RX_ARES 96 +#define GCC_UNIPHY_TX_ARES 97 +#define GCC_USB0_BCR 98 +#define GCC_USB0_PHY_BCR 99 +#define GCC_WCSS_BCR 100 +#define GCC_WCSS_DBG_ARES 101 +#define GCC_WCSS_ECAHB_ARES 102 +#define GCC_WCSS_ACMT_ARES 103 +#define GCC_WCSS_DBG_BDG_ARES 104 +#define GCC_WCSS_AHB_S_ARES 105 +#define GCC_WCSS_AXI_M_ARES 106 +#define GCC_WCSS_AXI_S_ARES 107 +#define GCC_WCSS_Q6_BCR 108 +#define GCC_WCSSAON_RESET 109 +#define GCC_UNIPHY_SOFT_RESET 110 +#define GCC_GEPHY_MISC_ARES 111 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h index 738e56aead93..d4264db2a07f 100644 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (c) 2021 Rockchip Electronics Co. Ltd. * Copyright (c) 2022 Collabora Ltd. diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index d78e38690ceb..eaf4a0d84f6a 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright (C) 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ @@ -151,4 +152,63 @@ #define JH7110_AONRST_END 8 +/* STGCRG resets */ +#define JH7110_STGRST_SYSCON 0 +#define JH7110_STGRST_HIFI4_CORE 1 +#define JH7110_STGRST_HIFI4_AXI 2 +#define JH7110_STGRST_SEC_AHB 3 +#define JH7110_STGRST_E24_CORE 4 +#define JH7110_STGRST_DMA1P_AXI 5 +#define JH7110_STGRST_DMA1P_AHB 6 +#define JH7110_STGRST_USB0_AXI 7 +#define JH7110_STGRST_USB0_APB 8 +#define JH7110_STGRST_USB0_UTMI_APB 9 +#define JH7110_STGRST_USB0_PWRUP 10 +#define JH7110_STGRST_PCIE0_AXI_MST0 11 +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 +#define JH7110_STGRST_PCIE0_AXI_SLV 13 +#define JH7110_STGRST_PCIE0_BRG 14 +#define JH7110_STGRST_PCIE0_CORE 15 +#define JH7110_STGRST_PCIE0_APB 16 +#define JH7110_STGRST_PCIE1_AXI_MST0 17 +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 +#define JH7110_STGRST_PCIE1_AXI_SLV 19 +#define JH7110_STGRST_PCIE1_BRG 20 +#define JH7110_STGRST_PCIE1_CORE 21 +#define JH7110_STGRST_PCIE1_APB 22 + +#define JH7110_STGRST_END 23 + +/* ISPCRG resets */ +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 +#define JH7110_ISPRST_M31DPHY_HW 2 +#define JH7110_ISPRST_M31DPHY_B09_AON 3 +#define JH7110_ISPRST_VIN_APB 4 +#define JH7110_ISPRST_VIN_PIXEL_IF0 5 +#define JH7110_ISPRST_VIN_PIXEL_IF1 6 +#define JH7110_ISPRST_VIN_PIXEL_IF2 7 +#define JH7110_ISPRST_VIN_PIXEL_IF3 8 +#define JH7110_ISPRST_VIN_SYS 9 +#define JH7110_ISPRST_VIN_P_AXI_RD 10 +#define JH7110_ISPRST_VIN_P_AXI_WR 11 + +#define JH7110_ISPRST_END 12 + +/* VOUTCRG resets */ +#define JH7110_VOUTRST_DC8200_AXI 0 +#define JH7110_VOUTRST_DC8200_AHB 1 +#define JH7110_VOUTRST_DC8200_CORE 2 +#define JH7110_VOUTRST_DSITX_DPI 3 +#define JH7110_VOUTRST_DSITX_APB 4 +#define JH7110_VOUTRST_DSITX_RXESC 5 +#define JH7110_VOUTRST_DSITX_SYS 6 +#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 +#define JH7110_VOUTRST_DSITX_TXESC 8 +#define JH7110_VOUTRST_HDMI_TX_HDMI 9 +#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 +#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 + +#define JH7110_VOUTRST_END 12 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 4ffa7c3612e6..9071f139649f 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h index f8001cf50bf1..79e52aca5912 100644 --- a/include/dt-bindings/reset/sun20i-d1-ccu.h +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2020 huangzhenwei@allwinnertech.com * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h index d93d6423d283..e20babc990af 100644 --- a/include/dt-bindings/reset/sun20i-d1-r-ccu.h +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> */ diff --git a/include/dt-bindings/reset/sun50i-a100-ccu.h b/include/dt-bindings/reset/sun50i-a100-ccu.h index 55c0ada99885..d13764bc1860 100644 --- a/include/dt-bindings/reset/sun50i-a100-ccu.h +++ b/include/dt-bindings/reset/sun50i-a100-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> */ diff --git a/include/dt-bindings/reset/sun50i-a100-r-ccu.h b/include/dt-bindings/reset/sun50i-a100-r-ccu.h index 737bf6f66626..1e7c4431f03c 100644 --- a/include/dt-bindings/reset/sun50i-a100-r-ccu.h +++ b/include/dt-bindings/reset/sun50i-a100-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> */ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h index 81106f455097..d038ddfa4818 100644 --- a/include/dt-bindings/reset/sun50i-h6-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h index 7950e799c76d..d541ade884fc 100644 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index cb6285a8d128..1bd8bb0a11be 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ |