diff options
Diffstat (limited to 'sound/soc/sof/intel/mtl.c')
| -rw-r--r-- | sound/soc/sof/intel/mtl.c | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 10298532816f..7452a7dbb0e4 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -90,8 +90,16 @@ static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) { + struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; struct sof_ipc4_msg *msg_data = msg->msg_data; + if (hda_ipc4_tx_is_busy(sdev)) { + hdev->delayed_ipc_tx_msg = msg; + return 0; + } + + hdev->delayed_ipc_tx_msg = NULL; + /* send the message via mailbox */ if (msg_data->data_size) sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, @@ -385,7 +393,7 @@ static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); - /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ + /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ usleep_range(1000, 1010); ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, @@ -414,7 +422,7 @@ static int mtl_power_down_dsp(struct snd_sof_dev *sdev) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, MTL_HFDSSCS_SPA_MASK, 0); - /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ + /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ usleep_range(1000, 1010); /* poll with timeout to check if operation successful */ @@ -492,11 +500,13 @@ static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) { struct sof_ipc4_msg notification_data = {{ 0 }}; struct snd_sof_dev *sdev = context; + bool ack_received = false; bool ipc_irq = false; u32 hipcida; u32 hipctdr; hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); + hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); /* reply message from DSP */ if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { @@ -507,9 +517,9 @@ static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) mtl_ipc_dsp_done(sdev); ipc_irq = true; + ack_received = true; } - hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { /* Message from DSP (reply or notification) */ u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); @@ -530,6 +540,7 @@ static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) spin_lock_irq(&sdev->ipc_lock); snd_sof_ipc_get_reply(sdev); + mtl_ipc_host_done(sdev); snd_sof_ipc_reply(sdev, data->primary); spin_unlock_irq(&sdev->ipc_lock); @@ -546,9 +557,9 @@ static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) sdev->ipc->msg.rx_data = ¬ification_data; snd_sof_ipc_msgs_rx(sdev); sdev->ipc->msg.rx_data = NULL; - } - mtl_ipc_host_done(sdev); + mtl_ipc_host_done(sdev); + } ipc_irq = true; } @@ -558,6 +569,13 @@ static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); } + if (ack_received) { + struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; + + if (hdev->delayed_ipc_tx_msg) + mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg); + } + return IRQ_HANDLED; } @@ -641,6 +659,9 @@ int sof_mtl_ops_init(struct snd_sof_dev *sdev) ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; + /* External library loading support */ + ipc4_data->load_library = hda_dsp_ipc4_load_library; + /* set DAI ops */ hda_set_dai_drv_ops(sdev, &sof_mtl_ops); @@ -663,6 +684,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE_ACE, .sdw_alh_base = SDW_ALH_BASE_ACE, + .d0i3_offset = MTL_HDA_VS_D0I3C, .check_sdw_irq = mtl_dsp_check_sdw_irq, .check_ipc_irq = mtl_dsp_check_ipc_irq, .cl_init = mtl_dsp_cl_init, |