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-rw-r--r--tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json63
1 files changed, 61 insertions, 2 deletions
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
index 1cc39aa032e1..12baf768ad8d 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
@@ -7,6 +7,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
@@ -18,17 +19,55 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.",
+ "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
+ "PEBScounters": "0,1,2,3,4,5",
+ "SampleAfterValue": "1000003",
+ "Speculative": "1",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
+ "PEBScounters": "0,1,2,3,4,5",
+ "SampleAfterValue": "2000003",
+ "Speculative": "1",
+ "UMask": "0x80",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
+ "PEBScounters": "0,1,2,3,4,5",
+ "SampleAfterValue": "200003",
+ "Speculative": "1",
+ "UMask": "0xe",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
+ "Speculative": "1",
"UMask": "0x90",
"Unit": "cpu_atom"
},
@@ -40,6 +79,7 @@
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
@@ -52,6 +92,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
@@ -63,6 +104,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
@@ -74,6 +116,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
@@ -85,6 +128,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
@@ -96,6 +140,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
@@ -107,6 +152,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
@@ -118,6 +164,7 @@
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
@@ -130,6 +177,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
@@ -141,6 +189,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
@@ -152,6 +201,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
@@ -163,6 +213,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
@@ -174,6 +225,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
@@ -185,6 +237,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
@@ -196,6 +249,7 @@
"EventName": "ITLB_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
@@ -208,6 +262,7 @@
"EventName": "ITLB_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
@@ -219,6 +274,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
@@ -230,6 +286,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
@@ -241,6 +298,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
@@ -252,7 +310,8 @@
"EventName": "ITLB_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
+ "Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
}
-] \ No newline at end of file
+]
generated by cgit (git 2.34.1) at 2024-06-19 20:42:36 +0000