diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json index c8de548b78fa..4645e9d3f460 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -1,5 +1,15 @@ [ { + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x82", @@ -9,6 +19,16 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x84", @@ -18,6 +38,16 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x88", @@ -164,35 +194,5 @@ "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts", "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" } ]
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