diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sapphirerapids/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sapphirerapids/other.json | 68 |
1 files changed, 67 insertions, 1 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json index 7d6f8e25bb10..95dbef8ae80a 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json @@ -7,6 +7,7 @@ "EventName": "ASSISTS.PAGE_FAULT", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8" }, { @@ -16,6 +17,7 @@ "EventName": "EXE.AMX_BUSY", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2" }, { @@ -173,6 +175,17 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", @@ -206,6 +219,17 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", @@ -342,10 +366,51 @@ "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", + "EventName": "RS.EMPTY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS_EMPTY.COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", "EventName": "RS_EMPTY.CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor.", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x7" }, { @@ -357,6 +422,7 @@ "EventName": "XQ.FULL_CYCLES", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1" } ] |