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AgeCommit message (Expand)Author
2015-11-18drm/i915: Reduce PSR re-activation time for VLV/CHV.Rodrigo Vivi
2015-11-18drm/i915: Delay first PSR activation.Rodrigo Vivi
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä
2015-11-18drm/i915: Add 'offset' to uncore funcsVille Syrjälä
2015-11-18drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+Ville Syrjälä
2015-11-18drm/i915: Turn vgpu pdps into an arrayVille Syrjälä
2015-11-18drm/i915: Wrap context LRI init in a macroVille Syrjälä
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä
2015-11-18drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä
2015-11-18drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä
2015-11-18drm/i915: s/0x50/RING_PSMI_CTL/Ville Syrjälä
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä
2015-11-18drm/i915: Streamline gpio_mmio_base deductionVille Syrjälä
2015-11-18drm/i915: Store DVO SRCDIM register offset under intel_dvo_deviceVille Syrjälä
2015-11-18drm/i915: s/is_sdvob/enum port/Ville Syrjälä
2015-11-18drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to i...Ville Syrjälä
2015-11-18pci: Decouple quirks.c from i915_reg.hVille Syrjälä
2015-11-18drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_p...Rodrigo Vivi
2015-11-18drm/i915: Stop tracking last calculated Sink CRC.Rodrigo Vivi
2015-11-18drm/i915: Make Sink crc calculation waiting for counter to reset.Rodrigo Vivi
2015-11-18drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.Rodrigo Vivi
2015-11-17drm/i915/skl: Remove unused suspend and resume callbacksPatrik Jakobsson
2015-11-17drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson
2015-11-17drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson
2015-11-17drm/i915: Add a modeset power domainPatrik Jakobsson
2015-11-17drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson
2015-11-17drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä
2015-11-17drm/i915: Introduce a gmbus power domainVille Syrjälä
2015-11-17drm/i915: Clean up AUX power domain handlingVille Syrjälä
2015-11-17drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson
2015-11-17drm/i915: Don't trust CSR program memory contentsPatrik Jakobsson
2015-11-17drm/i915: fix handling of the disable_power_well module optionImre Deak
2015-11-17drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak
2015-11-17drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLKImre Deak
2015-11-17drm/i915/skl: disable DC states before display core init/uninitImre Deak
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak
2015-11-17drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak
2015-11-17drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak
2015-11-17drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau
2015-11-17drm/i915: fix lookup_power_well for power wells without any domainImre Deak
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak
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