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Comment about the use of currently unconfigured MPP pins.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add pwm-fan support for controlling the fan speed, which allows the fan
speed to be controlled via sysfs. Alternatively, users can also add
their cooling maps to DT which will be specific to the environment that
they house the Macchiatobin, as well as their fan setup. For example,
one may connect PWM controlled case fans to this connector, and use
the PWM signal to control the case fans.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add cooling maps suitable for a Noctua NF-A4/10 fan attached to the
heat sink. The fan will toggle between two speeds in operation which
seems to be normal behaviour. More fine-grained steps may help to
reduce this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add pwm-fan support for controlling the fan speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add PWM support to the GPIO blocks.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support for PWM devices on the Armada 8k, which are useful on the
Macchiatobin and Clearfog GT 8K platforms for controlling the fan
speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Honour deferred probing for devm_clk_get() so that we can get the clock
for PWM.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvebu's pwm support to use regmap to access the registers to
prepare the driver to support the "blink" support on CP110.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The period of a PWM signal is the sum of the on and off durations. The
calculation being used by gpio-mvebu is not correct, resulting in the
period being miscalculated and invalid. Fix this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The resume operation of mvebu xHCI host have some issues,
so The XHCI_RESET_ON_RESUME quirk is added for it.
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Tested-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Lior Amsalem <alior@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Split out the code handling the GMAC from the rest of the driver. This
block appears to be shared amongst several revisions of the IP.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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An initial stab at converting mvneta to PCS operations. There's a few
FIXMEs to be solved.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Move the 1ms clock control out of mac_config() into mac_prepare() and
mac_finish(), which simplifies the mac_config() code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvneta to use the mac_prepare() and mac_finish() methods in
preparation to converting mvneta to split-PCS support.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Program the 1ms autonegotiation clock divisor according to the clocking
rate of neta - without this, the 1ms clock ticks at about 660us on
Armada 38x configured for 250MHz. Bring this into correct specification.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Further augmentation of the comphy setup.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The mvneta hardware appears to lock up in various random ways when
repeatedly switching speeds between 1G and 2.5G, which involves
reprogramming the COMPHY. It is not entirely clear why this happens,
but best guess is that reprogramming the COMPHY glitches mvneta clocks
causing the hardware to fail. It seems that rebooting resolves the
failure, but not down/up cycling the interface alone.
Various other approaches have been tried, such as trying to cleanly
power down the COMPHY and then take it back through the power up
initialisation, but this does not seem to help.
It was finally noticed that u-boot's last step when configuring a
COMPHY for "SGMII" mode was to poke at a register described as
"GBE_CONFIGURATION_REG", which is undocumented in any external
documentation. All that we have is the fact that u-boot sets a bit
corresponding to the "SGMII" lane at the end of COMPHY initialisation.
Experimentation shows that if we clear this bit prior to changing the
speed, and then set it afterwards, mvneta does not suffer this problem
on the SolidRun Clearfog when switching speeds between 1G and 2.5G.
This problem was found while script-testing phylink.
This fix also requires the corresponding change to DT to be effective.
See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
speeds".
Fixes: 14dc100b4411 ("phy: armada38x: add common phy support")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Update the Marvell Armada 38x COMPHY binding with an additional
optional register pair describing the location of an undocumented
system register controlling something to do with the Gigabit Ethernet
and COMPHY. There is one bit for each COMPHY lane that may be using
the serdes, but exactly what this register does is completely unknown.
This register only appears to exist on Armada 38x devices, and not
other SoCs using the NETA ethernet block, so it seems logical that it
should be part of the COMPHY.
This is also how u-boot groups this register; it is dealt with as part
of the COMPHY initialisation there.
However, at the end of the day, due to the undocumented nature of this
register, we can only guess.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The implementation appears not to support pause modes on anything
but RGMII, RGMII_TXID, MII and REVMII interface modes. Let phylink
know that detail.
(This may not be correct; particularly see the FIXMEs in this patch.)
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Use the phy interface mode bitmaps for SFP modules and PHYs to select
the operating interface for SFPs and PHYs with SFPs.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a supported_interfaces member to phylib so we know which
interfaces a PHY supports. Currently, set any unconverted driver
to indicate all interfaces are supported.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Select the host interface configuration according to the capabilities
of the host; this allows the kernel to support SFP modules using the
88x3310.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Pass the supported PHY interface types to phylib so that PHY drivers
can select an appropriate host configuration mode for their interface
according to the host capabilities.
This is only done for SFP modules presently.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Fill in the phy interface mode bitmap for the Marvell mvpp2 driver, so
phylink can know which interfaces are supported by the MAC.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Fill in the phy interface mode bitmap for the Marvell mvneta driver, so
phylink can know which interfaces are supported by the MAC.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Where a MAC provides the PHY interface mode capabilities, use the PHY
interface mode bitmaps to select the operating interface mode for
optical SFP modules, rather than using the linkmode bitmaps.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a PHY interface bitmap for the MAC driver to specify which PHY
interfaces are supported to phylink.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add parsing the SFP EEPROM to supported phy interface modes.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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DSA assumes that a bridge which has vlan filtering disabled is not
vlan aware, and ignores all vlan configuration. However, the kernel
software bridge code allows configuration in this state.
This causes the kernel's idea of the bridge vlan state and the
hardware state to disagree, so "bridge vlan show" indicates a correct
configuration but the hardware lacks all configuration. Even worse,
enabling vlan filtering on a DSA bridge immediately blocks all traffic
which, given the output of "bridge vlan show", is very confusing.
Provide an option that drivers can set to indicate they want to receive
vlan configuration even when vlan filtering is disabled. This is safe
for Marvell DSA bridges, which do not look up ingress traffic in the
VTU if the port is in 8021Q disabled state. Whether this change is
suitable for all DSA bridges is not known.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Display SFP module information verbosely, splitting the generic parts
into a separate file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a compatible for SFP+ cages. SFP+ cages are backwards compatible,
but the ethernet device behind them may not support the slower speeds
of SFP modules.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add debugfs support to SFP so that the internal state of the SFP state
machines and hardware signal state can be viewed from userspace, rather
than having to compile a debug kernel to view state state transitions
in the kernel log. The 'state' output looks like:
Module state: empty
Module probe attempts: 0 0
Device state: up
Main state: down
Fault recovery remaining retries: 5
PHY probe remaining retries: 12
moddef0: 0
rx_los: 1
tx_fault: 1
tx_disable: 1
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Cooled SFP+ transceivers need a longer initialisation (startup) time.
Select the initialisation time depending on the cooled option bit.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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phy_error() is called from phy_interrupt() or phy_state_machine(), and
uses WARN_ON() to print a backtrace. The backtrace is not useful when
reporting a PHY error.
However, a system may contain multiple ethernet PHYs, and phy_error()
gives no clue which one caused the problem.
Replace WARN_ON() with a call to phydev_err() so that we can see which
PHY had an error, and also inform the user that we are halting the PHY.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Allow the PHY to probe when there is no firmware, but do not allow the
link to come up by forcing the PHY state to PHY_HALTED in a similar way
to phy_error().
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Provide phy driver start/stop hooks so that the PHY driver knows when
the network driver is starting or stopping. This will be used for the
Marvell 10G driver so that we can sanely refuse to start if the PHYs
firmware is not present, and also so that we can sanely support SFPs
behind the PHY.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Support reporting the hardware resolved pause enablement states via
phylib, overriding our software implementation.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Allow phylib drivers to pass the hardware-resolved pause state to MAC
drivers, rather than using the software-based pause resolution code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Configure the Macchiatobin 10G PHY LED modes to correct their polarity.
We keep the existing LED behaviours, but switch their polarity to
reflect how they are connected. Tweak the LED modes as well to be:
left: off = no link
solid green = RJ45 link up (not SFP+ cage)
flash green = traffic
right: off = no link
solid green = 10G
solid yellow = 1G
flash green = 100M
flash yellow = 10M
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support for configuring the LEDs. Macchiatobin has an oddity in
that the left LED goes out when the cable is connected, and flashes
when there's link activity. This is because the reset default for
the LED outputs assume that the LED is connected to supply, not to
ground. Add support for configuring the LED modes and polarities.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a DT bindings document for the Marvell 10G driver, which will
augment the generic ethernet PHY binding by having LED mode
configuration.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support for the downshift tunable for the Marvell 88x3310 PHY.
Downshift is only usable with firmware 0.3.5.0 and later.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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There are several places which open code comparing PHY IDs. Provide a
couple of helpers to assist with this, using a slightly simpler test
than the original:
- phy_id_compare() compares two arbitary PHY IDs and a mask of the
significant bits in the ID.
- phydev_id_compare() compares the bound phydev with the specified
PHY ID, using the bound driver's mask.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The at803x driver contains a function, at803x_match_phy_id(), which
tests whether the PHY ID matches the value passed, comparing phy_id
with phydev->phy_id and testing all bits that have a "one" in the
mask, phydev->drv->phy_id_mask.
This is the same test that is used to match the driver, with phy_id
replaced with the driver specified ID, phydev->drv->phy_id.
Hence, we already know the value of the bits being tested if we look
at phydev->drv->phy_id directly, and we do not require a complicated
test to check them. Test directly against phydev->drv->phy_id instead.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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If we intend to use PCS operations, mac_pcs_get_state() will not be
implemented, so will be NULL. If we also intend to register the PCS
operations in mac_prepare() or mac_config(), then this leads to an
attempt to call NULL function pointer during phylink_start(). Avoid
this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Reason: A lot of the ptp drivers - which implement hardware time stamping - need
specific fields such as the sequence id from the ptp v2 header. Currently all
drivers implement that themselves.
Introduce a generic function to retrieve a pointer to the start of the ptp v2
header.
Suggested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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