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The "link status" interrupt is used for more than just link status.
Restructure mvpp2_link_status_isr() so we can add additional handling.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Check whether the MAC driver has implemented the get_ts_info()
method first, and call it if present. If this method returns
-EOPNOTSUPP, defer to the phylib or default implementation.
XXX: review any drivers that use phylib and provide get_ts_info().
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Split the XLG and GMAC PCS implementations and switch between them
during the mac_prepare() method.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvpp2 to phylink's new pcs support.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Move the GMAC reset handling into mac_prepare() / mac_finish()
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Ensure that the port is forced down while reconfiguring, controlling
this via mac_prepare() and mac_finish() so that it is down while we
are configuring our (future) PCS.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvpp2 to use the mac_prepare() and mac_finish() methods in
preparation to converting mvpp2 to split-PCS support.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Tidy up the ACPI hack so that we can minimise the function prototypes
for this. This avoids adding further prototypes unnecessarily.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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This commit is to tell the 0-day builder to avoid building this branch.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Use in-band-status for the SGMII PHY on Macchiatobin platforms.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The I2C1 bus on early mcbin hardware is mis-wired, swapping SCL and SDA.
Work around this by using the i2c-gpio driver instead. XXX Caught early
and this commit should be removed for mainline. XXX
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add the pinctrl settings and interrupts for the 10G PHYs.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add several pinctrls for functions brought out to connectors but not yet
usable with the core DT description.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Comment about the use of currently unconfigured MPP pins.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add pwm-fan support for controlling the fan speed, which allows the fan
speed to be controlled via sysfs. Alternatively, users can also add
their cooling maps to DT which will be specific to the environment that
they house the Macchiatobin, as well as their fan setup. For example,
one may connect PWM controlled case fans to this connector, and use
the PWM signal to control the case fans.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add cooling maps suitable for a Noctua NF-A4/10 fan attached to the
heat sink. The fan will toggle between two speeds in operation which
seems to be normal behaviour. More fine-grained steps may help to
reduce this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add pwm-fan support for controlling the fan speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add PWM support to the GPIO blocks.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support for PWM devices on the Armada 8k, which are useful on the
Macchiatobin and Clearfog GT 8K platforms for controlling the fan
speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Honour deferred probing for devm_clk_get() so that we can get the clock
for PWM.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvebu's pwm support to use regmap to access the registers to
prepare the driver to support the "blink" support on CP110.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The period of a PWM signal is the sum of the on and off durations. The
calculation being used by gpio-mvebu is not correct, resulting in the
period being miscalculated and invalid. Fix this.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The resume operation of mvebu xHCI host have some issues,
so The XHCI_RESET_ON_RESUME quirk is added for it.
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Tested-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Lior Amsalem <alior@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Split out the code handling the GMAC from the rest of the driver. This
block appears to be shared amongst several revisions of the IP.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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An initial stab at converting mvneta to PCS operations. There's a few
FIXMEs to be solved.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Move the 1ms clock control out of mac_config() into mac_prepare() and
mac_finish(), which simplifies the mac_config() code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvneta to use the mac_prepare() and mac_finish() methods in
preparation to converting mvneta to split-PCS support.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Program the 1ms autonegotiation clock divisor according to the clocking
rate of neta - without this, the 1ms clock ticks at about 660us on
Armada 38x configured for 250MHz. Bring this into correct specification.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Further augmentation of the comphy setup.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The mvneta hardware appears to lock up in various random ways when
repeatedly switching speeds between 1G and 2.5G, which involves
reprogramming the COMPHY. It is not entirely clear why this happens,
but best guess is that reprogramming the COMPHY glitches mvneta clocks
causing the hardware to fail. It seems that rebooting resolves the
failure, but not down/up cycling the interface alone.
Various other approaches have been tried, such as trying to cleanly
power down the COMPHY and then take it back through the power up
initialisation, but this does not seem to help.
It was finally noticed that u-boot's last step when configuring a
COMPHY for "SGMII" mode was to poke at a register described as
"GBE_CONFIGURATION_REG", which is undocumented in any external
documentation. All that we have is the fact that u-boot sets a bit
corresponding to the "SGMII" lane at the end of COMPHY initialisation.
Experimentation shows that if we clear this bit prior to changing the
speed, and then set it afterwards, mvneta does not suffer this problem
on the SolidRun Clearfog when switching speeds between 1G and 2.5G.
This problem was found while script-testing phylink.
This fix also requires the corresponding change to DT to be effective.
See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
speeds".
Fixes: 14dc100b4411 ("phy: armada38x: add common phy support")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Update the Marvell Armada 38x COMPHY binding with an additional
optional register pair describing the location of an undocumented
system register controlling something to do with the Gigabit Ethernet
and COMPHY. There is one bit for each COMPHY lane that may be using
the serdes, but exactly what this register does is completely unknown.
This register only appears to exist on Armada 38x devices, and not
other SoCs using the NETA ethernet block, so it seems logical that it
should be part of the COMPHY.
This is also how u-boot groups this register; it is dealt with as part
of the COMPHY initialisation there.
However, at the end of the day, due to the undocumented nature of this
register, we can only guess.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The implementation appears not to support pause modes on anything
but RGMII, RGMII_TXID, MII and REVMII interface modes. Let phylink
know that detail.
(This may not be correct; particularly see the FIXMEs in this patch.)
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Use the phy interface mode bitmaps for SFP modules and PHYs to select
the operating interface for SFPs and PHYs with SFPs.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a supported_interfaces member to phylib so we know which
interfaces a PHY supports. Currently, set any unconverted driver
to indicate all interfaces are supported.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Select the host interface configuration according to the capabilities
of the host; this allows the kernel to support SFP modules using the
88x3310.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Pass the supported PHY interface types to phylib so that PHY drivers
can select an appropriate host configuration mode for their interface
according to the host capabilities.
This is only done for SFP modules presently.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Fill in the phy interface mode bitmap for the Marvell mvpp2 driver, so
phylink can know which interfaces are supported by the MAC.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Fill in the phy interface mode bitmap for the Marvell mvneta driver, so
phylink can know which interfaces are supported by the MAC.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Where a MAC provides the PHY interface mode capabilities, use the PHY
interface mode bitmaps to select the operating interface mode for
optical SFP modules, rather than using the linkmode bitmaps.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a PHY interface bitmap for the MAC driver to specify which PHY
interfaces are supported to phylink.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add parsing the SFP EEPROM to supported phy interface modes.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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DSA assumes that a bridge which has vlan filtering disabled is not
vlan aware, and ignores all vlan configuration. However, the kernel
software bridge code allows configuration in this state.
This causes the kernel's idea of the bridge vlan state and the
hardware state to disagree, so "bridge vlan show" indicates a correct
configuration but the hardware lacks all configuration. Even worse,
enabling vlan filtering on a DSA bridge immediately blocks all traffic
which, given the output of "bridge vlan show", is very confusing.
Provide an option that drivers can set to indicate they want to receive
vlan configuration even when vlan filtering is disabled. This is safe
for Marvell DSA bridges, which do not look up ingress traffic in the
VTU if the port is in 8021Q disabled state. Whether this change is
suitable for all DSA bridges is not known.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Display SFP module information verbosely, splitting the generic parts
into a separate file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a compatible for SFP+ cages. SFP+ cages are backwards compatible,
but the ethernet device behind them may not support the slower speeds
of SFP modules.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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