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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add the PHY interface mode to the LPI methods and validate that LPI
is being entered for a supported mode.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add the PHY interface mode to the LPI methods and validate that LPI
is being entered for a supported mode.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Ass the PHY interface mode into mac_disable_tx_lpi() and
mac_enable_tx_lpi() methods.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Handle -EOPNOTSUPP from mac_enable_tx_lpi() to print a sensible error.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Select the initial SFP PHY interface mode from the PHY supported
interface bitmaps.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a supported_interfaces member to phylib so we know which
interfaces a PHY supports. Currently, set any unconverted driver
to indicate all interfaces are supported.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Display SFP module information verbosely, splitting the generic parts
into a separate file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a compatible for SFP+ cages. SFP+ cages are backwards compatible,
but the ethernet device behind them may not support the slower speeds
of SFP modules.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Cooled SFP+ transceivers need a longer initialisation (startup) time.
Select the initialisation time depending on the cooled option bit.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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phy_error() is called from phy_interrupt() or phy_state_machine(), and
uses WARN_ON() to print a backtrace. The backtrace is not useful when
reporting a PHY error.
However, a system may contain multiple ethernet PHYs, and phy_error()
gives no clue which one caused the problem.
Replace WARN_ON() with a call to phydev_err() so that we can see which
PHY had an error, and also inform the user that we are halting the PHY.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Allow the PHY to probe when there is no firmware, but do not allow the
link to come up by forcing the PHY state to PHY_HALTED in a similar way
to phy_error().
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Provide phy driver start/stop hooks so that the PHY driver knows when
the network driver is starting or stopping. This will be used for the
Marvell 10G driver so that we can sanely refuse to start if the PHYs
firmware is not present, and also so that we can sanely support SFPs
behind the PHY.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Support reporting the hardware resolved pause enablement states via
phylib, overriding our software implementation.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Allow phylib drivers to pass the hardware-resolved pause state to MAC
drivers, rather than using the software-based pause resolution code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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If MDIO_USXGMII_LINK is not set, it means that the PHYs media side
link is down. Indicate back to phylink that the link as a whole is
down.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Configure the Macchiatobin 10G PHY LED modes to correct their polarity.
We keep the existing LED behaviours, but switch their polarity to
reflect how they are connected. Tweak the LED modes as well to be:
left: off = no link
solid green = RJ45 link up (not SFP+ cage)
flash green = traffic
right: off = no link
solid green = 10G
solid yellow = 1G
flash green = 100M
flash yellow = 10M
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support for configuring the LEDs. Macchiatobin has an oddity in
that the left LED goes out when the cable is connected, and flashes
when there's link activity. This is because the reset default for
the LED outputs assume that the LED is connected to supply, not to
ground. Add support for configuring the LED modes and polarities.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add a DT bindings document for the Marvell 10G driver, which will
augment the generic ethernet PHY binding by having LED mode
configuration.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The modalias string provided in the uevent sysfs file does not conform
to the format used in PHY driver modules. One of the reasons is that
udev loading of PHY driver modules has not been an expected use case.
This patch changes the MODALIAS entry for only PHY devices from:
MODALIAS=of:Nethernet-phyT(null)
to:
MODALIAS=mdio:00000000001000100001010100010011
Other MDIO devices (such as DSA) remain as before.
However, having udev automatically load the module has the advantage
of making use of existing functionality to have the module loaded
before the device is bound to the driver, thus taking advantage of
multithreaded boot systems, potentially decreasing the boot time.
However, this patch will not solve any issues with the driver module
not being loaded prior to the network device needing to use the PHY.
This is something that is completely out of control of any patch to
change the uevent mechanism.
Reported-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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The hardware timestamps for packets contain a truncated seconds field,
only containing two bits of seconds. In order to provide the full
number of seconds, we need to keep track of the full hardware clock by
reading it every two seconds.
However, if we fail to read the clock, we silently ignore the error.
Print a warning indicating that the PP2 TAI clock timestamps have
become unreliable.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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No driver now uses the DSA switch phylink members, so we can now remove
the shim functions and method pointers. Arrange to print an error
message and fail registration if a DSA driver does not provide the
phylink MAC operations structure.
Signed-off-by: Russell King (oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add phylink EEE control methods to allow EEE to be configured. When
LPI is to be disabled, we force the port to have EEE disabled, but
when enabling EEE, if the port is under the control of the PPU, we
stop forcing it, otherwise we force-enable EEE.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add support for EEE forcing using the MAC control register. Replace
the 88e6393x errata 4.5 EEE disable code with a call to the new EEE
forcing code.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add a port_set_eee() method to allow the EEE settings for a port to be
configured.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Older XPCS IP requires SGMII_LINK and PHY_SIDE_SGMII to be set when
operating in 1000BASE-X mode even though the XPCS is not configured for
SGMII. An example of a device with older XPCS IP is KSZ9477.
We already don't clear these bits if we switch from SGMII to 1000BASE-X
on TXGBE - which would result in 1000BASE-X with the PHY_SIDE_SGMII bit
left set.
It is currently believed to be safe to set both bits on newer IP
without side-effects.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Older revisions of the XPCS IP do not support the MAC_AUTO_SW flag and
need the BMCR register updated with the speed information from the PHY.
Split the DW_XPCS_SGMII_MODE_MAC mode into _AUTO and _MANUAL variants,
where _AUTO mode means the update happens in hardware autonomously,
whereas the _MANUAL mode means that we need to update the BMCR register
when the link comes up.
This will be required for the older XPCS IP found in KSZ9477.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add SGMII mode setting which configures whether XPCS immitates the MAC
end of the link or the PHY end, and in the latter case, where the data
for generating the link's configuration word comes from. This ties up
all the register bits necessary to configure this mode into one
control.
Set this to PHY_HW mode for TXGBE.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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When in SGMII mode, the hardware can be configured to use either 4-bit
or 8-bit MII connection. Currently, we don't change this bit for most
implementations with the exception of TXGBE requiring 8-bit. Move this
decision to the creation code and act on it when configuring SGMII.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Use the generic stmmac_set_clk_tx_rate() to configure the MAC transmit
clock.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Use the generic stmmac_set_clk_tx_rate() to configure the MAC transmit
clock.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Place register number definitions immediately above their field
definitions and order by register number.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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We only need to enable the MAC receiver and transmiter only when the
link has come up.
With commit "net: stmmac: move phylink_resume() after resume setup
is complete" we move the race between stmmac_mac_link_up() and
stmmac_hw_setup(), ensuring that stmmac_mac_link_up() happens
afterwards. This patch is a pre-requisit of this change.
Remove the unnecessary call to stmmac_mac_set(, true) in
stmmac_hw_setup().
Tested-by: Furong Xu <0x1207@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Remove fiddling with _TE and _RE in the GMAC control register in the
start_tx/stop_tx/start_rx/stop_rx() methods as this should be handled
by stmmac_mac_link_up() and stmmac_mac_link_down() and not during
initialisation.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Furong Xu <0x1207@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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stmmac_release() calls phylink_stop() and then goes on to call
stmmac_mac_set(, false). However, phylink_stop() will call
stmmac_mac_link_down() before returning, which will do this work.
Remove this unnecessary call.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Furong Xu <0x1207@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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While the network device is registered, it is published to userspace,
and thus userspace can change its state. This means calling
functions such as stmmac_stop_all_dma() and stmmac_mac_set() are
racy.
Moreover, unregister_netdev() will unpublish the network device, and
then if appropriate call the .ndo_stop() method, which is
stmmac_release(). This will first call phylink_stop() which will
synchronously take the link down, resulting in stmmac_mac_link_down()
and stmmac_mac_set(, false) being called.
stmmac_release() will also call stmmac_stop_all_dma().
Consequently, neither of these two functions need to called prior
to unregister_netdev() as that will safely call paths that will
result in this work being done if necessary.
Remove these redundant racy calls.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Furong Xu <0x1207@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Phylink does not permit drivers to mess with the netif carrier, as
this will de-synchronise phylink with the MAC driver. Moreover,
setting and clearing the TE and RE bits via stmmac_mac_set() in this
path is also wrong as the link may not be up.
Replace the netif_carrier_on(), netif_carrier_off() and
stmmac_mac_set() calls with the appropriate phylink_start() and
phylink_stop() calls, thereby allowing phylink to manage the netif
carrier and TE/RE bits through the .mac_link_up() and .mac_link_down()
methods.
Note that RE should only be set after the DMA is ready to avoid the
receive FIFO between the MAC and DMA blocks overflowing, so
phylink_start() needs to be placed after DMA has been started.
Tested-by: Furong Xu <0x1207@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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The Synopsys Designwavre GMAC core databook requires all clocks to be
active in order to complete software reset.
This means if the PHY receive clock has been stopped due to the media
being in EEE low-power state, and the PHY being permitted to stop its
clock, then software reset will not complete.
Phylink now provides a way to work around this by calling
phylink_prepare_resume() before attempting to issue a reset. This will
prepare any attached PHY by disabling its permission to stop the clock.
phylink_resume() will restore the receive clock stop setting according
to the configuration passed from the netdev driver.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Move phylink_resume() to be after the setup in stmmac_resume() has
completed, as phylink_resume() may result in an immediate call to the
.mac_link_up method, which will enable the transmitter and receiver,
and enable the transmit queues.
This behaviour has been witnessed by Jon Hunter on the Jetson TX2
platform (Tegra 186).
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Currently, the calls to phylink's suspend and resume functions are
inside overly complex tests, and boil down to:
if (device_may_wakeup(priv->device) && priv->plat->pmt) {
call phylink
} else {
call phylink and
if (device_may_wakeup(priv->device))
do something else
}
This results in phylink always being called, possibly with differing
arguments for phylink_suspend().
Simplify this code, noting that each site is slightly different due to
the order in which phylink is called and the "something else".
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add a resume preparation function, which will ensure that the receive
clock from the PHY is appropriately configured while resuming.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Add configuration of the receive clock-stop in phylink_resume() to
ensure that the clock-stop is correctly configured.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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