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2023-02-16phy: rockchip-typec: Fix unsigned comparison with less than zeroJiapeng Chong
The dp and ufp are defined as bool type, the return value type of function extcon_get_state should be int, so the type of dp and ufp are modified to int. ./drivers/phy/rockchip/phy-rockchip-typec.c:827:12-14: WARNING: Unsigned expression compared with zero: dp > 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3962 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20230213035709.99027-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-14Merge tag 'phy-fixes-6.2' into nextVinod Koul
Merge fixes tag pulled into mainline by Linus into phy/next due to dependency on amlogic patches
2023-02-14phy: rockchip-typec: fix tcphy_get_mode error caseNeill Kapron
The existing logic in tcphy_get_mode() can cause the phy to be incorrectly configured to USB UFP or DisplayPort mode when extcon_get_state returns an error code. extcon_get_state() can return 0, 1, or a negative error code. It is possible to get into the failing state with an extcon driver which does not support the extcon connector id specified as the second argument to extcon_get_state(). tcphy_get_mode() ->extcon_get_state() -->find_cable_index_by_id() --->return -EINVAL; Fixes: e96be45cb84e ("phy: Add USB Type-C PHY driver for rk3399") Signed-off-by: Neill Kapron <nkapron@google.com> Reviewed-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230126001013.3707873-1-nkapron@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-13phy: qcom: snps-eusb2: Add missing headersVinod Koul
The driver was missing to include couple of headers explictly which causes build to fail on other archs drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_snps_eusb2_hsphy_write_mask': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:147:15: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration] 147 | reg = readl_relaxed(base + offset); | ^~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:150:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration] 150 | writel_relaxed(reg, base + offset); | ^~~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_eusb2_default_parameters': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:161:42: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 161 | FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); | ^~~~~~~~~~ Fix this by adding bitfield.h and iopoll.h explictly Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp-combo: Add support for SM8550Abel Vesa
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: Add v6 DP register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-usb: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatibleAbel Vesa
Add the SM8550 compatible to the list. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom: Add QCOM SNPS eUSB2 driverAbel Vesa
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10dt-bindings: phy: Add qcom,snps-eusb2-phy schema fileAbel Vesa
The SM8550 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema for the new driver. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEsAbel Vesa
Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550Abel Vesa
Document the QMP PCIe PHY compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom: com-qmp-combo: add SM8350 & SM8450 supportNeil Armstrong
Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10dt-bindings: phy: qcom,qmp-usb3-dp: document sm8350 & sm8450 compatibleNeil Armstrong
Document the USB3/DP Combo PHY compatible found on the SM8350 & SM8450 SoCs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-1-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03phy: qcom-qmp: Introduce Kconfig symbols for discrete driversStephen Boyd
Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03dt-bindings: phy: tegra-xusb: Add support for Tegra234Jon Hunter
Add the compatible string for the Tegra234 XUSB PHY. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230111110450.24617-3-jonathanh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03Merge tag 'phy-devm_of_phy_optional_get' into nextVinod Koul
Merge tag phy-devm_of_phy_optional_get into next to bring in the new devm_of_phy_optional_get() API and users
2023-02-03usb: host: ohci-exynos: Convert to devm_of_phy_optional_get()Geert Uytterhoeven
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. This lets us drop several checks for IS_ERR(), as phy_power_{on,off}() handle NULL parameters fine. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/3adc5dd1149a17ea7daf4463549feab886c6b145.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03usb: host: ehci-exynos: Convert to devm_of_phy_optional_get()Geert Uytterhoeven
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. This lets us drop several checks for IS_ERR(), as phy_power_{on,off}() handle NULL parameters fine. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/a28baf4e07e464c43aff9e52263b5a902f5da9a0.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03PCI: tegra: Convert to devm_of_phy_optional_get()Geert Uytterhoeven
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/56508eeadf7fa8692877e872871f10294d48c49d.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03net: lan966x: Convert to devm_of_phy_optional_get()Geert Uytterhoeven
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/993b0f4ac5b84b2b72223011614d2e821f9e7302.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03net: fman: memac: Convert to devm_of_phy_optional_get()Geert Uytterhoeven
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/f2d801cd73cca36a7162819289480d7fc91fcc7e.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03phy: Add devm_of_phy_optional_get() helperGeert Uytterhoeven
Add an optional variant of devm_of_phy_get() that also takes care of printing real errors, so drivers no longer have to open-code this operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4cd0069bcff424ffc5c3a102397c02370b91985b.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03doc: phy: Document devm_of_phy_get()Geert Uytterhoeven
Add the missing documentation for devm_of_phy_get(), which was forgotten when the function was introduced. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/768d5845668f081620098a0b4479d1481e212bac.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-03phy: Remove unused phy_optional_get()Geert Uytterhoeven
There were never any upstream users of this function since its introduction almost 10 years ago. Besides, the dummy for phy_optional_get() should have returned NULL instead of an error code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/df61992b1d66bccf4e6e1eafae94a7f7d7629f34.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp-combo: Add config for SM6350Luca Weiss
Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-2-4d700a90ba16@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatibleLuca Weiss
Add the compatible describing the combo phy found on SM6350. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-1-4d700a90ba16@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: mediatek: remove temporary variable @mask_Chunfeng Yun
Remove the temporary @mask_, this may cause build warning when use clang compiler for powerpc, but can't reproduce it when compile for arm64. the build warning is caused by: "warning: result of comparison of constant 18446744073709551615 with expression of type (aka 'unsigned long') is always false [-Wtautological-constant-out-of-range-compare]" More information provided in below lore link. After removing @mask_, there is a "CHECK:MACRO_ARG_REUSE" when run checkpatch.pl, but due to @mask is constant, no reuse problem will happen. Link: https://lore.kernel.org/lkml/202212160357.jJuesD8n-lkp@intel.com/t/ Fixes: 84513eccd678 ("phy: mediatek: fix build warning of FIELD_PREP()") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118084343.26913-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp-ufs: Add SM8550 supportAbel Vesa
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: pcs-ufs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: qserdes-txrx: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: qserdes-com: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02dt-bindings: phy: Add QMP UFS PHY comptible for SM8550Abel Vesa
Document the QMP UFS PHY compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-31phy: phy-can-transceiver: Add support for NXP TJR1443Geert Uytterhoeven
The NXP TJR1443 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1043. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/0bfa1e4c43632e49c9512b4e7daa970545545dcf.1674037830.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-20dt-bindings: phy: ti,tcan104x-can: Document NXP TJR1443Geert Uytterhoeven
The NXP TJR1443 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1043. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/6ee5e2ce00019bd3f77d6a702b38bab1a45f3bb0.1674037830.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: phy-can-transceiver: Skip warning if no "max-bitrate"Geert Uytterhoeven
According to the DT bindings, the "max-bitrate" property is optional. However, when it is not present, a warning is printed. Fix this by adding a missing check for -EINVAL. Fixes: a4a86d273ff1b6f7 ("phy: phy-can-transceiver: Add support for generic CAN transceiver driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/88e158f97dd52ebaa7126cd9631f34764b9c0795.1674037334.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18dt-bindings: phy: g12a-usb2-phy: fix compatible string documentationHeiner Kallweit
The compatible strings in the driver don't have the meson prefix. Fix this in the documentation and rename the file accordingly. Fixes: da86d286cce8 ("dt-bindings: phy: meson-g12a-usb2-phy: convert to yaml") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/8d960029-e94d-224b-911f-03e5deb47ebc@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18dt-bindings: phy: g12a-usb3-pcie-phy: fix compatible string documentationHeiner Kallweit
The compatible string in the driver doesn't have the meson prefix. Fix this in the documentation and rename the file accordingly. Fixes: 87a55485f2fc ("dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/0a82be92-ce85-da34-9d6f-4b33034473e5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18dt-bindings: phy: tegra-xusb: Convert to json-schemaThierry Reding
Convert the Tegra XUSB pad controller bindings from free-form text format to json-schema. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230113150804.1272555-1-thierry.reding@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qcom-qmp-usb: fix the regs layout table for sdx65 uniphy PHYDmitry Baryshkov
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use qmp_v5_usb3phy_regs_layout, to remove possible confusion. Fixes: 14d98d3bf70e ("phy: qcom-qmp-usb: fix regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212138.421583-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHYDmitry Baryshkov
The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove possible confusion. Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212138.421583-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qcom-qmp-combo: rework regs layout arraysDmitry Baryshkov
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qcom-qmp-combo: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov
The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit (git 2.34.1) at 2025-06-03 18:51:35 +0000