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2024-03-02clk: qcom: gcc-ipq5018: fix terminating of frequency table arraysGabor Juhos
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-1-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16clk: qcom: dispcc-sdm845: Adjust internal GDSC wait timesKonrad Dybcio
SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6 Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controllerDmitry Baryshkov
This clock controller has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the bindings now after dropping the driver itself. Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240216-drop-sc7180-mss-v1-2-0a8dc8d71c0c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16clk: qcom: drop the SC7180 Modem subsystem clock driverDmitry Baryshkov
This driver has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the driver to remove possible confusion. Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240216-drop-sc7180-mss-v1-1-0a8dc8d71c0c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14clk: qcom: Use qcom_branch_set_clk_en()Konrad Dybcio
Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-2-5b79eb7278b2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14clk: qcom: branch: Add a helper for setting the enable bitKonrad Dybcio
We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-1-5b79eb7278b2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco constSatya Priya Kakitapalli
The clk_init_data and pll_vco structures are never modified, make them const. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240201-dispcc-sm8150-v1-1-cbeb89015e5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8180x: Add missing UFS QREF clocksManivannan Sadhasivam
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into ↵Bjorn Andersson
clk-for-6.9 Merge the two SC8180X reset defines through a topic branch, to allow them being picked up in the DeviceTree source tree as well.
2024-02-07clk: qcom: gcc-msm8953: add more resetsVladimir Lypak
Add new entries in the gcc driver for some more resets found on MSM8953. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> [luca: expand commit message, move entry, add more entries] Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240125-msm8953-mdss-reset-v2-2-fd7824559426@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into ↵Bjorn Andersson
clk-for-6.9 Merge MSM8953 GCC DeviceTree binding update through topic branch, to allow it to be merged into DeviceTree source tree as well.
2024-02-07clk: qcom: videocc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register video clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-4-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gpucc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register GPU clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-3-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: dispcc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register display clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-2-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: camcc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register camera clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-1-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-18-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-17-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-16-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-15-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8150: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-14-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8650: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The Venus hw on 8650 is similar to the one on 8550, follow its requirements. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-13-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-12-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-11-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-10-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-9-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm7150: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-8-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm4450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 4450 being somewhat close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-7-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8280 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-6-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8180x: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-5-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sa8775p: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-4-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: reset: Ensure write completion on reset de/assertionKonrad Dybcio
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c8ac6 ("clk: qcom: Add reset controller support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-3-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Add missing UFS QREF clocksManivannan Sadhasivam
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: gcc-msm8953: add more resetsVladimir Lypak
Add new defines for some more BCRs found on MSM8953. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> [luca: expand commit message, add more resets] Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Commonize the de/assert functionsKonrad Dybcio
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-2-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Increase max reset delayKonrad Dybcio
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-1-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add camcc clock driver for x1e80100Rajendra Nayak
Add the camcc clock driver for x1e80100 Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add TCSR clock driver for x1e80100Abel Vesa
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add GPU clock driver for x1e80100Rajendra Nayak
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-8-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add dispcc clock driver for x1e80100Rajendra Nayak
Add the dispcc clock driver for x1e80100. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-7-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06Merge branch ↵Bjorn Andersson
'20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9 Merge X1E clock bindings through a topic branch, to make the defines available for inclusion in DeviceTree branches as well.
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Camera Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock ControllerAbel Vesa
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-4-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 GPU Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-3-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Display Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-2-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: Drop the SM8650 DISPCC dedicated schemaAbel Vesa
The block is the same between these platforms, at least from devicetree point of view. So drop the dedicated schema and use the SM8550 one instead. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-1-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02dt-bindings: clock: qcom: Fix @codeaurora email in Q6SSTOPJeffrey Hugo
The servers for the @codeaurora domain are long retired and any messages addressed there will bounce. Govind Singh has left the company which appears to leave the Q6SSTOP clock controller binding unmaintained. Move maintenance of the binding to the Qualcomm Clock Drivers maintainer as suggested by Bjorn Andersson. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240202171915.4101842-1-quic_jhugo@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gpucc-sc8280xp: Add external supply for GX gdscBjorn Andersson
On SA8295P and SA8540P the GFX rail is powered by a dedicated external regulator, instead of the rpmh-controlled "gfx.lvl". Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-3-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gdsc: Enable supply reglator in GPU GX handlerBjorn Andersson
The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-2-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30dt-bindings: clock: qcom: Allow VDD_GFX supply to GXBjorn Andersson
In some designs the SoC's VDD_GFX pads are supplied by an external regulator, rather than a power-domain. Allow this to be described in the GPU clock controller binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-1-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-04-03 10:05:41 +0000