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In order to add meta-schema checks for additional/unevaluatedProperties
being present, all schema need to make this explicit. As the top-level
board/SoC schemas always have additional properties, add
'additionalProperties: true'.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201005183830.486085-4-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
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Add properties: #address-cells, #size-cells and ranges. Due to the
Hisilicon CPU controller node may contains child nodes, change the value
of "additionalProperties" from "false" to "type: object".
The corresponding examples are also added.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20201012061225.1597-11-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Add properties: #reset-cells, #address-cells, #size-cells and ranges. Due
to the Hisilicon system controller node may contains child nodes, change
the value of "additionalProperties" from "false" to "type: object". The
examples have also been updated.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20201012061225.1597-10-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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json-schema
Convert the Hisilicon Hi6220 domain controllers binding to DT schema
format using json-schema. All of them are grouped into one yaml file, to
help users understand differences and avoid repeated descriptions.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200930031712.2365-16-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
controller binding to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-18-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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to json-schema
Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-17-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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json-schema
Convert the Hisilicon Bootwrapper boot method binding to DT schema format
using json-schema.
The property boot-method contains two groups of physical address range
information: bootwrapper and relocation. The "uint32-array" type is not
suitable for it, because the field "address" and "size" may occupy one or
two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it
can be written in "<addr size addr size>" or "<addr size>, <addr size>"
format.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-15-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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json-schema
Convert the Hisilicon Fabric controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-14-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Convert the Hisilicon peripheral misc control register binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-13-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Convert the Hisilicon CPU controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-12-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Convert the Hisilicon system controller and its variants binding to DT
schema format using json-schema. All of them are grouped into one yaml
file, to help users understand differences and avoid repeated
descriptions.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-11-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Add devicetree binding for Hisilicon SD5203 SoC.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-6-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Convert Hisilicon SoC bindings to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
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separate file
Split the devicetree bindings of each Hisilicon controller from
hisilicon.txt into a separate file, the file name is the compatible name
attach the .txt file name extension.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-4-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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The compatible strings of Hi6220 SRAM controller, HiP05/HiP06 PCIe-SAS
subsystem controller, HiP05/HiP06 PERI subsystem controller and
HiP05/HiP06 DSA subsystem controller is in syscon.yaml now.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-3-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
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Several DT references got broken due to txt->yaml conversion.
Those are auto-fixed by running:
scripts/documentation-file-ref-check --fix
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
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Add devicetree binding for HiKey970 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add devicetree binding for Hi3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- move pci_uevent_ers() out of pci.h (Michael Ellerman)
- skip ASPM common clock warning if BIOS already configured it (Sinan
Kaya)
- fix ASPM Coverity warning about threshold_ns (Gustavo A. R. Silva)
- remove last user of pci_get_bus_and_slot() and the function itself
(Sinan Kaya)
- add decoding for 16 GT/s link speed (Jay Fang)
- add interfaces to get max link speed and width (Tal Gilboa)
- add pcie_bandwidth_capable() to compute max supported link bandwidth
(Tal Gilboa)
- add pcie_bandwidth_available() to compute bandwidth available to
device (Tal Gilboa)
- add pcie_print_link_status() to log link speed and whether it's
limited (Tal Gilboa)
- use PCI core interfaces to report when device performance may be
limited by its slot instead of doing it in each driver (Tal Gilboa)
- fix possible cpqphp NULL pointer dereference (Shawn Lin)
- rescan more of the hierarchy on ACPI hotplug to fix Thunderbolt/xHCI
hotplug (Mika Westerberg)
- add support for PCI I/O port space that's neither directly accessible
via CPU in/out instructions nor directly mapped into CPU physical
memory space. This is fairly intrusive and includes minor changes to
interfaces used for I/O space on most platforms (Zhichang Yuan, John
Garry)
- add support for HiSilicon Hip06/Hip07 LPC I/O space (Zhichang Yuan,
John Garry)
- use PCI_EXP_DEVCTL2_COMP_TIMEOUT in rapidio/tsi721 (Bjorn Helgaas)
- remove possible NULL pointer dereference in of_pci_bus_find_domain_nr()
(Shawn Lin)
- report quirk timings with dev_info (Bjorn Helgaas)
- report quirks that take longer than 10ms (Bjorn Helgaas)
- add and use Altera Vendor ID (Johannes Thumshirn)
- tidy Makefiles and comments (Bjorn Helgaas)
- don't set up INTx if MSI or MSI-X is enabled to align cris, frv,
ia64, and mn10300 with x86 (Bjorn Helgaas)
- move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick
Lawler)
- merge pcieport_if.h into portdrv.h (Bjorn Helgaas)
- move workaround for BIOS PME issue from portdrv to PCI core (Bjorn
Helgaas)
- completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas)
- remove portdrv link order dependency (Bjorn Helgaas)
- remove support for unused VC portdrv service (Bjorn Helgaas)
- simplify portdrv feature permission checking (Bjorn Helgaas)
- remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn
Helgaas)
- remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas)
- use cached AER capability offset (Frederick Lawler)
- don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg)
- rename pcie-dpc.c to dpc.c (Bjorn Helgaas)
- use generic pci_mmap_resource_range() instead of powerpc and xtensa
arch-specific versions (David Woodhouse)
- support arbitrary PCI host bridge offsets on sparc (Yinghai Lu)
- remove System and Video ROM reservations on sparc (Bjorn Helgaas)
- probe for device reset support during enumeration instead of runtime
(Bjorn Helgaas)
- add ACS quirk for Ampere (née APM) root ports (Feng Kan)
- add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas
Vincent-Cross)
- protect device restore with device lock (Sinan Kaya)
- handle failure of FLR gracefully (Sinan Kaya)
- handle CRS (config retry status) after device resets (Sinan Kaya)
- skip various config reads for SR-IOV VFs as an optimization
(KarimAllah Ahmed)
- consolidate VPD code in vpd.c (Bjorn Helgaas)
- add Tegra dependency on PCI_MSI_IRQ_DOMAIN (Arnd Bergmann)
- add DT support for R-Car r8a7743 (Biju Das)
- fix a PCI_EJECT vs PCI_BUS_RELATIONS race condition in Hyper-V host
bridge driver that causes a general protection fault (Dexuan Cui)
- fix Hyper-V host bridge hang in MSI setup on 1-vCPU VMs with SR-IOV
(Dexuan Cui)
- fix Hyper-V host bridge hang when ejecting a VF before setting up MSI
(Dexuan Cui)
- make several structures static (Fengguang Wu)
- increase number of MSI IRQs supported by Synopsys DesignWare bridges
from 32 to 256 (Gustavo Pimentel)
- implemented multiplexed IRQ domain API and remove obsolete MSI IRQ
API from DesignWare drivers (Gustavo Pimentel)
- add Tegra power management support (Manikanta Maddireddy)
- add Tegra loadable module support (Manikanta Maddireddy)
- handle 64-bit BARs correctly in endpoint support (Niklas Cassel)
- support optional regulator for HiSilicon STB (Shawn Guo)
- use regulator bulk API for Qualcomm apq8064 (Srinivas Kandagatla)
- support power supplies for Qualcomm msm8996 (Srinivas Kandagatla)
* tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (123 commits)
MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver
HISI LPC: Add ACPI support
ACPI / scan: Do not enumerate Indirect IO host children
ACPI / scan: Rename acpi_is_serial_bus_slave() for more general use
HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings
of: Add missing I/O range exception for indirect-IO devices
PCI: Apply the new generic I/O management on PCI IO hosts
PCI: Add fwnode handler as input param of pci_register_io_range()
PCI: Remove __weak tag from pci_register_io_range()
MAINTAINERS: Add missing /drivers/pci/cadence directory entry
fm10k: Report PCIe link properties with pcie_print_link_status()
net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
net/mlx5: Report PCIe link properties with pcie_print_link_status()
net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
PCI: Add pcie_print_link_status() to log link speed and whether it's limited
PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
misc: pci_endpoint_test: Handle 64-bit BARs properly
PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly
PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing
PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar
...
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The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of
peripherals.
Implement the LPC host controller driver which performs the I/O operations
on the underlying hardware. We don't want to touch existing drivers such
as ipmi-bt, so this driver applies the indirect-IO introduced in the
previous patch after registering an indirect-IO node to the indirect-IO
devices list which will be searched by the I/O accessors to retrieve the
host-local I/O port.
The driver config is set as a bool instead of a tristate. The reason here
is that, by the very nature of the driver providing a logical PIO range, it
does not make sense to have this driver as a loadable module. Another more
specific reason is that the Huawei D03 board which includes Hip06 SoC
requires the LPC bus for UART console, so should be built in.
Tested-by: dann frazier <dann.frazier@canonical.com>
Signed-off-by: Zou Rongrong <zourongrong@huawei.com>
Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Rob Herring <robh@kernel.org> # dts part
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It adds bindings doc for Hi3798CV200 peripheral controller.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Add bindings for HiKey960 Board.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add binding for hisilicon Hi3660 SoC and HiKey960 Board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip07 D05 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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The Hip05 and Hip06 are very similar in design, use better and unified
name for system controller.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add device tree bindings for Hi3519 system controller.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip06 D03 board.
Meanwhile, reorder the soc/board name alphabetically.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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When linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
mdio_bus mdio@803c0000: mdio sys ctl reg has not maped"
The source code about the subctrl is dealt syscon, but dts doesn't.
It cause such fault, so this patch adds the syscon info on dts files to
fixes it.
Signed-off-by: Kejian Yan <yankejian@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As usual, this is the massive branch we have for each release. Lots
of various updates and additions of hardware descriptions on existing
hardware, as well as the usual additions of new boards and SoCs.
This is also the first release where we've started mixing 64- and
32-bit DT updates in one branch.
(Specific details on what's actually here and new is pretty easy to
tell from the diffstat, so there's little point in duplicating listing
it here)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
ARM: dts: uniphier: add system-bus-controller nodes
ARM64: juno: disable NOR flash node by default
ARM: dts: uniphier: add outer cache controller nodes
arm64: defconfig: Enable PCI generic host bridge by default
arm64: Juno: Add support for the PCIe host bridge on Juno R1
Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
dts/ls2080a: Update Simulator DTS to add support of various peripherals
dts/ls2080a: Remove text about writing to Free Software Foundation
dts/ls2080a: Update DTSI to add support of various peripherals
doc: DTS: Update DWC3 binding to provide reference to generic bindings
doc/bindings: Update GPIO devicetree binding documentation for LS2080A
Documentation/dts: Move FSL board-specific bindings out of /powerpc
Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
arm64: Rename FSL LS2085A SoC support code to LS2080A
arm64: Use generic Layerscape SoC family naming
ARM: dts: uniphier: add ProXstream2 Vodka board support
ARM: dts: uniphier: add ProXstream2 Gentil board support
...
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Add PCIe host support for HiSilicon SoC Hip05, related DT binding
documentation, and maintainer update.
[bhelgaas: changelog, 32-bit only config write warning text]
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: liudongdong <liudongdong3@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org> (DT binding)
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This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Document "hisilicon,hi6220-sramctrl" for SRAM controller.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add dts file for Hisilicon hip01 ca9x2 board
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
[olof: Folded in smp enable-method from a different patch]
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add Hisilicon HiP04 SoC platform & Fabric controller.
Fabric controller could be used to configure snoop filter among multiple
clusters.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.
Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.
They are different in implementation such as SMP, IPs integarted and
earlycon configure.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Enable SMP support on hi3xxx platform
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Zhang Mingjun <zhang.mingjun@linaro.org>
Tested-by: Li Xin <li.xin@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fix checkpatch errors]
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Add board support with device tree for Hisilicon Hi3620 SoC platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fix checkpatch errors]
[khilman: fold in patch which selects GPIO in Kconfig]
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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