linux-arm.git - Russell King's ARM Linux kernel tree

Age	Commit message (Collapse)	Author
2023-04-04	dt-bindings: move cache controller bindings to a cache directory	Conor Dooley
	There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2014-02-22	ARM: MM: Add DT binding for Feroceon L2 cache	Andrew Lunn
	Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>