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2024-04-03dt-bindings: clock: ti: remove unstable remarkKrzysztof Kozlowski
Several TI SoC clock bindings were marked as work-in-progress / unstable between 2013-2016, for example in commit f60b1ea5ea7a ("CLK: TI: add support for gate clock"). It was enough of time to consider them stable and expect usual ABI rules. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20240224091236.10146-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2024-04-03dt-bindings: clock: keystone: remove unstable remarkKrzysztof Kozlowski
Keystone clock controller bindings were marked as work-in-progress / unstable in 2013 in commit b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") and commit 7affe5685c96 ("clk: keystone: Add gate control clock driver") Almost eleven years is enough, so drop the "unstable" remark and expect usual ABI rules. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240224091236.10146-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2024-03-15Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Not a ton of stuff happening in the clk framework. We got some more devm helpers and we seem to be going in the direction of "just turn this stuff on already and leave me alone!" with the addition of a devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that into a pmdomain that drivers attach instead, but this API should help drivers simplify in the meantime. Outside of the devm wrappers, we've got the usual clk driver updates that are dominated by the major phone SoC vendors (Samsung and Qualcomm) and the non-critical driver fixes for things like incorrect topology descriptions and wrong registers or bit fields. More details are below, but I'd say that it looks pretty ordinary. The only thing that really jumps out at me is the Renesas clk driver that's ignoring clks that are assigned to remote processors in DeviceTree. That's a new feature that they're using to avoid marking clks as CLK_IGNORE_UNUSED based on the configuration of the system. Core: - Increase dev_id len for clkdev lookups - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks for a device - Add a devm variant of clk_rate_exclusive_get() New Drivers: - Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1 Elite SoC - Google GS101 PERIC0 and PERIC1 clock controllers - Exynos850 PDMA clocks - Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock controllers Removed Drivers: - Remove the unused Qualcomm sc7180 modem clk driver Updates: - Fix some static checker errors in the Hisilicon clk driver - Polarfire MSSPLL hardware has 4 output clocks (the driver supported previously only one output); each of these 4 outputs feed dividers and the output of each divider feed individual hardware blocks (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to control their clocks thus clock driver support was added for all MSSPLL output clocks - Typo fixes in the Qualcomm IPQ5018 GCC driver - Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi - Properly terminate frequency tables in different Qualcomm clk drivers - Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953 - Add missing UFS CLKREF clks on Qualcomm SC8180X - Avoid significant delays during boot by adding a softdep on rpmhpd to Qualcomm SDM845 gcc driver - Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC driver - Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC driver - Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk driver - Switch display, GPU, video, and camera Qualcomm clk drivers to module_platform_driver() - Set a longer delay for Venus resets on many Qualcomm SoCs - Correct the GDSC wait times in the Qualcomm SDM845 display clk driver - Fix clock listing Oops on Amlogic axg - New pll-rate for Rockchip rk3568 - i2s rate improvements for Rockchip rk3399 - Rockchip rk3588 syscon clock fixes and removal of overall clock-number from the rk3588 binding header - A prerequisite for later improvements to the Rockchip rk3588 linked clocks - Minor clean-ups and error handling improvements in both composite-8m and SCU i.MX clock drivers - Fix for SAI_MCLK_SEL definition for i.MX8MP - Register the Samsung CMU MISC clock controller earlier, so the Multi Core Timer clocksource can use it on Google GS101 - Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI will get proper clock rates - Refactor the generic Samsung CPU clock controllers code, preparing it for supporting Exynos850 CPU clocks - Fix some clk kerneldoc warnings - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on Renesas R-Car V4M - Ignore all clocks which are assigned to a non-Linux system in the Renesas clk driver - Add watchdog clock on Renesas RZ/G3S - Add camera (CRU) clock and reset on Renesas RZ/G2UL - Add support for the Renesas R-Car V4M (R8A779H0) SoC - Convert some clk bindings to YAML so they can be validated" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) clk: zynq: Prevent null pointer dereference caused by kmalloc failure clk: fractional-divider: Use bit operations consistently clk: fractional-divider: Move mask calculations out of lock clk: Fix clk_core_get NULL dereference clk: starfive: jh7110-vout: Convert to platform remove callback returning void clk: starfive: jh7110-isp: Convert to platform remove callback returning void clk: imx: imx8-acm: Convert to platform remove callback returning void clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe() clk: Add a devm variant of clk_rate_exclusive_get() ...
2024-03-13Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and ↵Stephen Boyd
'clk-rate-exclusive' into clk-next - Increase dev_id len for clkdev lookups * clk-samsung: (25 commits) clk: samsung: Add CPU clock support for Exynos850 clk: samsung: Pass mask to wait_until_mux_stable() clk: samsung: Keep register offsets in chip specific structure clk: samsung: Keep CPU clock chip specific data in a dedicated struct clk: samsung: Pass register layout type explicitly to CLK_CPU() clk: samsung: Pass actual CPU clock registers base to CPU_CLK() clk: samsung: Group CPU clock functions by chip clk: samsung: Use single CPU clock notifier callback for all chips clk: samsung: Reduce params count in exynos_register_cpu_clock() clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c clk: samsung: Improve clk-cpu.c style dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 clk: samsung: gs101: add support for cmu_peric1 clk: samsung: gs101: drop extra empty line dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit clk: samsung: exynos850: Propagate SPI IPCLK rate change clk: samsung: gs101: gpio_peric0_pclk needs to be kept on clk: samsung: exynos850: Add PDMA clocks dt-bindings: clock: tesla,fsd: Fix spelling mistake clk: samsung: gs101: add support for cmu_peric0 ... * clk-imx: clk: imx: imx8mp: Fix SAI_MCLK_SEL definition clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev() clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite() clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection * clk-rockchip: clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent clk: rockchip: rk3588: use linked clock ID for GATE_LINK clk: rockchip: rk3588: fix indent clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf dt-bindings: clock: rk3588: add missing PCLK_VO1GRF dt-bindings: clock: rk3588: drop CLK_NR_CLKS clk: rockchip: rk3588: fix CLK_NR_CLKS usage clk: rockchip: rk3568: Add PLL rate for 128MHz * clk-clkdev: clkdev: Update clkdev id usage to allow for longer names * clk-rate-exclusive: clk: Add a devm variant of clk_rate_exclusive_get()
2024-03-13Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and ↵Stephen Boyd
'clk-microchip' into clk-next * clk-remove: clk: starfive: jh7110-vout: Convert to platform remove callback returning void clk: starfive: jh7110-isp: Convert to platform remove callback returning void clk: imx: imx8-acm: Convert to platform remove callback returning void * clk-amlogic: clk: meson: Add missing clocks to axg_clk_regmaps * clk-qcom: (62 commits) clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller clk: qcom: drop the SC7180 Modem subsystem clock driver clk: qcom: Use qcom_branch_set_clk_en() clk: qcom: branch: Add a helper for setting the enable bit clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks clk: qcom: gcc-msm8953: add more resets clk: qcom: videocc-*: switch to module_platform_driver ... * clk-parent: clk: Fix clk_core_get NULL dereference * clk-microchip: clk: microchip: mpfs: convert MSSPLL outputs to clk_divider clk: microchip: mpfs: add missing MSSPLL outputs clk: microchip: mpfs: setup for using other mss pll outputs clk: microchip: mpfs: split MSSPLL in two dt-bindings: can: mpfs: add missing required clock dt-bindings: clock: mpfs: add more MSSPLL output definitions
2024-03-13Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and ↵Stephen Boyd
'clk-allwinner' into clk-next * clk-aspeed: clk: ast2600: Add FSI parent clock with correct rate dt-bindings: clock: ast2600: Add FSI clock * clk-keystone: clk: keystone: sci-clk: Adding support for non contiguous clocks * clk-mobileye: dt-bindings: reset: mobileye,eyeq5-reset: add bindings dt-bindings: clock: mobileye,eyeq5-clk: add bindings clk: fixed-factor: add fwname-based constructor functions clk: fixed-factor: add optional accuracy support * clk-allwinner: clk: sunxi: usb: fix kernel-doc warnings clk: sunxi: sun9i-cpus: fix kernel-doc warnings clk: sunxi: a20-gmac: fix kernel-doc warnings
2024-03-13Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' ↵Stephen Boyd
and 'clk-bulk' into clk-next - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks for a device - Fix some static checker errors in the hisilicon clk driver * clk-renesas: (25 commits) clk: renesas: r8a779h0: Add RPC-IF clock clk: renesas: r8a779h0: Add SYS-DMAC clocks clk: renesas: r8a779h0: Add SDHI clock clk: renesas: r8a779h0: Add EtherAVB clocks clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux clk: renesas: r8a779f0: Correct PFC/GPIO parent clock clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks clk: renesas: r8a779h0: Add I2C clocks clk: renesas: r8a779h0: Add watchdog clock clk: renesas: r8a779h0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Fix PCIe clock name clk: renesas: cpg-mssr: Add support for R-Car V4M clk: renesas: rcar-gen4: Add support for FRQCRC1 clk: renesas: r9a07g043: Add clock and reset entries for CRU clk: renesas: r9a08g045: Add clock and reset support for watchdog dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support dt-bindings: power: Add r8a779h0 SYSC power domain definitions dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support ... * clk-cleanup: clk: zynq: Prevent null pointer dereference caused by kmalloc failure clk: fractional-divider: Use bit operations consistently clk: fractional-divider: Move mask calculations out of lock clk: ti: dpll3xxx: use correct function names in kernel-doc clk: clocking-wizard: Remove redundant initialization of pointer div_addr clk: keystone: sci-clk: match func name comment to actual clk: cdce925: Remove redundant assignment to variable 'rate' MAINTAINERS: drop Sekhar Nori * clk-hisilicon: clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc() clk: hisilicon: hi3559a: Fix an erroneous devm_kfree() clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister() * clk-mediatek: clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe() clk: mediatek: add infracfg reset controller for mt7988 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock dt-bindings: clock: mediatek: convert hifsys to the json-schema clock clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe() clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe() * clk-bulk: clk: Provide managed helper to get and enable bulk clocks
2024-03-01Merge tag 'qcom-arm64-for-6.9' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM64 DeviceTree updates for v6.9 Four variants of Samsung Galaxy Core Prime and Grand Prime, built on MSM8916, and the Hardware Development Kit (HDK) for SM8550, are introduced. On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P, TCSR, USB, display, audio, and soundwire support is introduced, and enabled across the CRD and QCP devices. For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is defined. Missing qlink-logging reserved-memory region is added for the modem remoteproc. FastRPC compute contexts are marked dma-coherent. Audio, USB Type-C and PM8010 support is introduced across MTP and QRD devices. GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X, SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550. UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP, SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650. PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SC7280, and SC8180X On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline Crypto Engine (ICE) is enabled for IPQ9574. On MSM8953 the GPU and its IOMMU is introduced, the reset for the display subsystem is also wired up. VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and SM6115. USB Type-C port management is enabled on QRB4210 RB2. On the SA8295P ADP the MAX20411 regulator powering the GPU rails is introduced and the GPU is enabled. The first PCI instance on SA8540P Ride is disabled for now, as a fix for the interrupt storm produced here has not been presented. On SA8775P the firmware memory map has changed and is updated. Safety IRQ is added to the Ethernet controller. On SC7180 UFS support is introduced and the cros-ec-spi is marked as wakeup source. For SC7280 capacity and DPC properties are added, cryptobam definition is improved to work in more firmware environments, more Chrome-specific properties are moved out from main dtsi, and cros-ec-spi is maked as a wakeup source. Slimbus definition is added to the platform. A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK and Venus are enabled. LEDs are introduced and voltage settings corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes and GCC protected clocks are introduced to make the board boot properly. RPMh sleep stats and a variety of cleanups and fixes are introduced for SC8180X. On SC8280XP the additional tsens instances are introduced. Camera Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp vadc channels are introduced on the CRD, to allow ADC channels to be tied to the shared PMIC temp-alarms, to actually report temperature. On SDM630 USB QMP PHY support is introduced and enabled on the Inforce IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled and configured. On SM6350 display subsystem interconnects and tsens-based thermal zones are added. On SM7125 UFS support is added. On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware paths are corrected. SM8150 PCIe controller definitions are corrected. As with SM8650, the SM8550 the fastrpc compute contexts are marked dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS controller frequency definition is moved to the generic opp-table. Touchscreen is enabled on the QRD device. As usual, a variety of smaller cleanups and corrections to match DeviceTree bindings and style guidelines are introduced across the various files. * tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (176 commits) arm64: dts: qcom: sm6115: fix USB PHY configuration arm64: dts: sm8650: Add msi-map-mask for PCIe nodes arm64: dts: qcom: replace underscores in node names dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE arm64: dts: qcom: pm4125: define USB-C related blocks arm64: dts: qcom: sa8540p-ride: disable pcie2a node arm64: dts: qcom: sc7280: add slimbus DT node arm64: dts: qcom: sc7280: Add capacity and DPC properties arm64: dts: qcom: pmi632: Add PBS client and use in LPG node arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 arm64: dts: qcom: sm8150: correct PCIe wake-gpios arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU arm64: dts: qcom: sm6350: Remove "disabled" state of GMU arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge arm64: dts: qcom: sm6350: Add interconnect for MDSS arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts arm64: dts: qcom: minor whitespace cleanup ... Link: https://lore.kernel.org/r/20240225050146.484422-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-29Merge tag 'samsung-dt64-6.9' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.9 Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding support for: 1. Multi Core Timer (MCT) clocksource. 2. Several clock controllers (DTS and DT bindings) and use new clocks in several other device nodes. 3. More serial-interface instances: USI8 and USI12 with I2C. Exynos850: 1. SPI and DMA controllers (PL330). * tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add fifosize for UART in Device Tree arm64: dts: exynos: gs101: minor whitespace cleanup arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole arm64: dts: exynos: gs101: define USI12 with I2C configuration arm64: dts: exynos: gs101: enable cmu-peric1 clock controller dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit arm64: dts: exynos: Add SPI nodes for Exynos850 arm64: dts: exynos: Add PDMA node for Exynos850 arm64: dts: exynos: gs101: use correct clocks for usi_uart arm64: dts: exynos: gs101: use correct clocks for usi8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock arm64: dts: exynos: gs101: enable eeprom on gs101-oriole arm64: dts: exynos: gs101: define USI8 with I2C configuration arm64: dts: exynos: gs101: update USI UART to use peric0 clocks arm64: dts: exynos: gs101: enable cmu-peric0 clock controller arm64: dts: exynos: gs101: remove reg-io-width from serial arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node dt-bindings: clock: exynos850: Add PDMA clocks dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-29Merge tag 'renesas-dts-for-v6.9-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.9 - Add GPIO keys and watchdog support for the RZ/G3S SMARC development board, - Add GNSS support for Renesas ULCB development boards equipped with the Shimafuji Kingfisher extension, - Add support for the standalone White Hawk CPU board, - Add support for the R-Car V4H ES2.0 (R8A779G2) SoC and the White Hawk Single development board, - Add initial support for the R-Car V4M (R8A779H0) SoC and the Gray Hawk Single development board, - Add camera support for the RZ/G2UL SoC, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits) arm64: dts: renesas: gray-hawk-single: Enable watchdog timer arm64: dts: renesas: r8a779h0: Add RWDT node arm64: dts: renesas: Improve TMU interrupt descriptions ARM: dts: renesas: Improve TMU interrupt descriptions arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes arm64: dts: renesas: Add Gray Hawk Single board support arm64: dts: renesas: Add Renesas R8A779H0 SoC support arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface arm64: dts: renesas: r9a08g045: Add watchdog node arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support dt-bindings: power: Add r8a779h0 SYSC power domain definitions dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support arm64: dts: renesas: r8a779g2: Add White Hawk Single support arm64: dts: renesas: Add Renesas R8A779G2 SoC support arm64: dts: renesas: white-hawk: Factor out common parts arm64: dts: renesas: white-hawk-cpu: Factor out common parts arm64: dts: renesas: white-hawk: Add SoC name to top-level comment arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards ... Link: https://lore.kernel.org/r/cover.1707487834.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-25dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1Sam Protsenko
Document CPU clock management unit compatibles and add corresponding clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for the new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-21dt-bindings: clock: mobileye,eyeq5-clk: add bindingsThéo Lebrun
Add DT schema bindings for the EyeQ5 clock controller driver. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-3-31d4ce3630c3@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clockRafał Miłecki
This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Dropped "syscon" as it was incorrectly used 3. Adjusted nodename, "compatible" and "reg" in example Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240214061233.24645-4-zajec5@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clockRafał Miłecki
This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Dropped "syscon" as it was incorrectly used 3. Adjusted nodename, "compatible" and "reg" in example Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240214061233.24645-3-zajec5@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21dt-bindings: clock: mediatek: convert hifsys to the json-schema clockRafał Miłecki
This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Documented "#reset-cells" property 3. Dropped "syscon" as it was incorrectly used 4. Adjusted "compatible" and "reg" in example Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240214061233.24645-2-zajec5@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-16dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controllerDmitry Baryshkov
This clock controller has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the bindings now after dropping the driver itself. Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240216-drop-sc7180-mss-v1-2-0a8dc8d71c0c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/clkKrzysztof Kozlowski
dt-bindings for Google GS101 clock controllers for v6.9 The Devicetree binding headers for Samsung Exynos and Google GS101 clock controllers, used by the Samsung clock controller drivers.
2024-02-07dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unitAndré Draszik
Add dt-schema documentation and clock IDs for the Connectivity Peripheral 1 (PERIC1) clock management unit. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240201161258.1013664-3-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-06Merge branch ↵Bjorn Andersson
'20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9 Merge the X1E clock binding topic branch, to gain access to the many clock defines.
2024-02-06Merge branch ↵Bjorn Andersson
'20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9 Merge X1E clock bindings through a topic branch, to make the defines available for inclusion in DeviceTree branches as well.
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Camera Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock ControllerAbel Vesa
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-4-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 GPU Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-3-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Display Clock ControllerRajendra Nayak
Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-2-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06dt-bindings: clock: Drop the SM8650 DISPCC dedicated schemaAbel Vesa
The block is the same between these platforms, at least from devicetree point of view. So drop the dedicated schema and use the SM8550 one instead. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-1-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-02dt-bindings: clock: qcom: Fix @codeaurora email in Q6SSTOPJeffrey Hugo
The servers for the @codeaurora domain are long retired and any messages addressed there will bounce. Govind Singh has left the company which appears to leave the Q6SSTOP clock controller binding unmaintained. Move maintenance of the binding to the Qualcomm Clock Drivers maintainer as suggested by Bjorn Andersson. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240202171915.4101842-1-quic_jhugo@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-31dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M supportGeert Uytterhoeven
Document support for the Clock Pulse Generator (CPG) and Module Standby Software Reset (MSSR) module on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/eb3cd02b62f3ca834df079a3f1e551d9414fe42a.1706194617.git.geert+renesas@glider.be
2024-01-30dt-bindings: clock: qcom: Allow VDD_GFX supply to GXBjorn Andersson
In some designs the SoC's VDD_GFX pads are supplied by an external regulator, rather than a power-domain. Allow this to be described in the GPU clock controller binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-1-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23dt-bindings: clock: tesla,fsd: Fix spelling mistakeVarada Pavani
Fix typo 'inteernal' to 'internal' in 'Documentation/devicetree/ bindings/clock/tesla,fsd-clock.yaml'. Signed-off-by: Varada Pavani <v.pavani@samsung.com> Link: https://lore.kernel.org/r/20231219115834.65720-1-v.pavani@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23Merge tag 'samsung-dt-bindings-clk-6.9-2' into next/clkKrzysztof Kozlowski
dt-bindings for Google GS101 clock controllers for v6.9 The Devicetree binding headers for Samsung Exynos and Google GS101 clock controllers, used by the Samsung clock controller drivers.
2024-01-23dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unitTudor Ambarus
Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0) clock management unit. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-22dt-bindings: clock: gcc-sc8180x: Add the missing CX power domainKonrad Dybcio
The GCC block is (mostly) powered by the VDD_CX rail. Allow specifying it in power-domains. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-1-93b5c107ed43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-22dt-bindings: clock: gs101: rename cmu_misc clock-namesTudor Ambarus
'bus' and 'ip' are sufficient because naming is local to the module. As the bindings have not made a release yet, rename the cmu_misc clock-names. Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240109114908.3623645-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-12Merge tag 'devicetree-for-6.8' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Convert FPGA bridge, all TPMs (finally), and Rockchip HDMI bindings to schemas - Improvements in Samsung GPU schemas - A few more cases of dropping unneeded quotes in schemas - Merge QCom idle-states txt binding into common idle-states schema - Add X1E80100, SM8650, SM8650, and SDX75 SoCs to QCom Power Domain Controller - Add NXP i.mx8dl to SCU PD - Add synaptics r63353 panel controller - Clarify the wording around the use of 'wakeup-source' property - Add a DTS coding style doc - Add smi vendor prefix - Fix DT_SCHEMA_FILES incorrect matching of paths outside the kernel tree - Disable sysfb (e.g. EFI FB) when simple-framebuffer node is present - Fix double free in of_parse_phandle_with_args_map() - A couple of kerneldoc fixes * tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (37 commits) of: unittest: Fix of_count_phandle_with_args() expected value message dt-bindings: fpga: altera: Convert bridge bindings to yaml dt-bindings: fpga: Convert bridge binding to yaml dt-bindings: vendor-prefixes: Add smi dt-bindings: power: Clarify wording for wakeup-source property of: Fix double free in of_parse_phandle_with_args_map dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES drivers: of: Fixed kernel doc warning dt-bindings: tpm: Document Microsoft fTPM bindings dt-bindings: tpm: Convert IBM vTPM bindings to DT schema dt-bindings: tpm: Convert Google Cr50 bindings to DT schema dt-bindings: tpm: Consolidate TCG TIS bindings dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible dt-bindings: arm: Add remote etm dt-binding dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas dt-bindings: display: panel: Add synaptics r63353 panel controller dt-bindings: arm: merge qcom,idle-state with idle-state dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries ...
2024-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2024-01-09Merge branch 'clk-rs9' into clk-nextStephen Boyd
* clk-rs9: clk: rs9: Add support for 9FGV0841 clk: rs9: Replace model check with bitshift from chip data clk: rs9: Limit check to vendor ID in VID register dt-bindings: clk: rs9: Add 9FGV0841
2024-01-09Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-nextStephen Boyd
- Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP * clk-zynq: drivers: clk: zynqmp: update divider round rate logic drivers: clk: zynqmp: calculate closest mux rate * clk-xilinx: clocking-wizard: Add support for versal clocking wizard dt-bindings: clock: xilinx: add versal compatible * clk-stm: dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform clk: stm32mp1: use stm32mp13 reset driver clk: stm32mp1: move stm32mp1 clock driver into stm32 directory
2024-01-09Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into ↵Stephen Boyd
clk-next * clk-imx: clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() dt-bindings: clock: support i.MX93 ANATOP clock module * clk-qcom: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ... * clk-amlogic: clk: meson: g12a: add CSI & ISP gates clocks clk: meson: g12a: add MIPI ISP clocks dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids * clk-mediatek: clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: brcm,kona-ccu: convert to YAML dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema dt-bindings: Remove alt_ref from versal
2024-01-09Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and ↵Stephen Boyd
'clk-sophgo' into clk-next - Add glitch free PLL setting support to si5351 clk driver * clk-versa: clk: versaclock3: Drop ret variable clk: versaclock3: Add missing space between ')' and '{' clk: versaclock3: Use u8 return type for get_parent() callback clk: versaclock3: Avoid unnecessary padding clk: versaclock3: Update vc3_get_div() to avoid divide by zero * clk-silabs: clk: si5351: allow PLLs to be adjusted without reset dt-bindings: clock: si5351: add PLL reset mode property dt-bindings: clock: si5351: convert to yaml * clk-samsung: clk: samsung: Improve kernel-doc comments clk: samsung: Fix kernel-doc comments * clk-starfive: clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro * clk-sophgo: dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
2024-01-03dt-bindings: clock: mediatek: add clock controllers of MT7988Daniel Golle
Add various clock controllers found in the MT7988 SoC to existing bindings (if applicable) and add files for the new ethwarp, mcusys and xfi-pll clock controllers not previously present in any SoC. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoCInochi Amaoto
Add definition for the clock controller of the CV1800 series SoC. For CV181X, it has a clock that CV180X does not have. To avoid misuse, also add a compatible string to identify CV181X series SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://github.com/milkv-duo/duo-files/blob/main/hardware/CV1800B/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-22Merge tag 'qcom-arm64-for-6.8' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM64 updates for v6.8 Support is added for the new Snapdragon 8 Gen 3 mobile platform, with support for the MTP and QRD development devices, the new Snapdragon X Elite compute platform with QCP and CRD development/references devices, the QCS6590/QCM6490 platform with support for the IDP development device and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset built on MSM8939, and Xiaomi Pad 6 on SM8250. On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one additional QUP SPI controller is added. CPU OPP tables are selectively enabled based on fuses, for both IPQ5332 and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes. Common elements of the IPQ9574 RDP boards are refactored into a common include file. IPQ9574 also gains description of its LEDs and WPS busttons. MSM8916 finally gets the DSP-based audio described, and this is enabled for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains notification LED, battery and charger support is added to Loncheer L8150, and GPU is enabled for Samsung Galaxy Tab A. Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is enabled as well. The Longcheer L9100 gains RGB notification LED support, and the wireless subsystem is enabled. Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is enabled, to allow using wakeup interrupts. Interconnect providers, MPM and display are added to QCM2290. UFS, remoteprocs and WiFi is enabled for Fairphone FP5. On Fairphone FP3 audio, WiFi and Bluetooth are enabled. On the Robotics RB1, HDMI and the CAN bus controller are added. On Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled. Bluetooth is enabled on the Robotics RB5. On SA8775P tsens and thermal is added, as well as the random number generator. Sound and RTC support is added for the Acer Aspire 1. On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices to inherit the base dtsi. Support for UFS, crypto, TrustZone based remoteprocs, the Camera Control Interface (CCI) and random number generator support are added. Additionally a variety of smaller fixes are introduced. A variety of fixes are introduced for SC8180X, in particular missing power-domains and interconnects. On SC8280XP the camera clock controller is added, and a number of smaller fixes are introduced. The display subsystem in SDM670 is described. On SDX75 interconnect providers are added, as is USB3 and the related PHY, which is then enabled on the IDP device. On SM6115 interconnect providers are added and existing clients are wired up. A UART controller is added as well. The MPM is added, to provide wakeup interrutps, on SM6375. The modem subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator supplies are corrected. On SM8150 the DisplayPort controller is added, for USB Type-C output, which together with the addition of HDMI is described on the HDK board. GPU and random number generator support are added to SM8450, and enabled on the HDK board. On SM8550 GPU, IPA, random number generator, missing SoundWire ports are added, and enabled on both MTP and QRD devices. Additionally a large number of smaller functional and DeviceTree binding validation issues are corrected across a variety of platforms. * tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (288 commits) arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting arm64: dts: qcom: sc8180x: Describe the GIC redistributor arm64: dts: qcom: sc8180x: Add interconnects to UFS arm64: dts: qcom: sc8180x: Add missing MDP clocks arm64: dts: qcom: sc8180x: Add UFS GDSC arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi arm64: dts: qcom: sc7280: Rename reserved-memory nodes arm64: dts: qcom: sc7280: Remove unused second MPSS reg arm64: dts: qcom: sdm670: add display subsystem arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY arm64: dts: qcom: sm8150: add DisplayPort controller arm64: dts: qcom: sm8150-hdk: fix SS USB regulators arm64: dts: qcom: sm8150-hdk: enable HDMI output arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes arm64: dts: qcom: sm8550-qrd: add PM8010 regulators arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators arm64: dts: qcom: qcm2290: Hook up MPM ... Link: https://lore.kernel.org/r/20231219145402.874161-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-12-21Merge tag 'mtk-dts64-for-v6.8' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt MediaTek ARM64 DeviceTree updates for v6.8 This adds devicetree bindings and nodes for: - Media Data Path 3 (MDP3) bindings and enablement on MT8195 - Smart Voltage Scaling (SVS) on MT8195 - LVTS SoC thermal on MT8192 - MT8188 SoC along with its resets, display bindings, and more - MT8183 hardware video decoder (mtk-vcodec-dec) Adds the following new machines: - MT8188 Evaluation Board (EVB) - MT8183 Chromebooks: Kukui-Katsu, Jacuzzi-Makomo, Pico, Pico6 Performs cleanups for various MediaTek SoCs and PMICs, and also includes some spare fixes. * tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (60 commits) arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0 arm64: dts: mt6358: Drop bogus "regulator-fixed" compatible properties arm64: dts: mt8183: kukui-jacuzzi: Drop bogus anx7625 panel_flag property arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile dt-bindings: soc: mediatek: pwrap: Modify compatible for MT8188 dt-bindings: arm: mediatek: Add mt8188 pericfg compatible dt-bindings: arm: Add compatible for MediaTek MT8188 arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes dt-bindings: display: mediatek: dsi: add compatible for MediaTek MT8195 arm64: dts: mediatek: mt6358: Merge ldo_vcn33_* regulators dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml arm64: dts: mediatek: mt8195: add MDP3 nodes arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes dt-bindings: display: mediatek: padding: add compatible for MT8195 dt-bindings: display: mediatek: split: add compatible for MT8195 ... Link: https://lore.kernel.org/r/20231212114515.121695-1-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-12-21Merge tag 'samsung-dt64-6.8' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.8 Two (and a half) major items are coming with this pull request: 1. Add specific compatibles to all Samsung Exynos and Tesla FSD blocks, because that's what guidelines expect [1] and is generally recommended practice. Existing compatibles are left untouched, thus no driver changes are needed. The work only cleans things up, so any future contributions will use recommended style: specific and fallback compatibles. Since no driver changes are needed in this work and the DTS is directly affected by bindings change (running tests with `make dtbs_check`), this pull includes all bindings changes, even though usual practice is that bindings come via driver subsystem. Keeping everything here makes review and testing easier. Also will allow us to avoid conflicts related to new platforms (see below). 2. Add ExynosAutov920 SoC and SADK board (Samsung Automotive Development Kit) with minimal support so far: serial console, GPIO-based keys and PWM fan. 3. Add few bindings for upcoming Google GS101 SoC. This pull request does not include its DTS yet, just few reviewed dependencies. DTS will be coming soon. [1] Documentation/devicetree/bindings/writing-bindings.rst * tag 'samsung-dt64-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (38 commits) arm64: dts: exynos: add minimal support for exynosautov920 sadk board arm64: dts: exynos: add initial support for exynosautov920 SoC dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible arm64: dts: fsd: add specific compatibles for Tesla FSD dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD dt-bindings: serial: samsung: add specific compatible for Tesla FSD dt-bindings: pwm: samsung: add specific compatible for Tesla FSD dt-bindings: i2c: exynos5: add specific compatible for Tesla FSD arm64: dts: exynosautov9: use Exynos7 fallbacks for pin wake-up controller arm64: dts: exynos850: use Exynos7 fallbacks for pin wake-up controllers dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatible dt-bindings: arm: samsung: Document exynosautov920 SADK board binding dt-bindings: pwm: samsung: add exynosautov920 compatible dt-bindings: serial: samsung: add exynosautov920-uart compatible dt-bindings: samsung: usi: add exynosautov920-usi compatible dt-bindings: samsung: exynos-pmu: add exynosautov920 compatible ... Link: https://lore.kernel.org/r/20231212093105.13938-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-12-17dt-bindings: clock: si5351: add PLL reset mode propertyAlvin Šipraga
For applications where the PLL must be adjusted without glitches in the clock output(s), a new silabs,pll-reset-mode property is added. It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Jacob Siverskog <jacob@teenage.engineering> Cc: Sergej Sawazki <sergej@taudac.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-2-69b82311cb90@bang-olufsen.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17dt-bindings: clock: si5351: convert to yamlAlvin Šipraga
The following additional properties are described: - clock-names - clock-frequency of the clkout child nodes In order to suppress warnings from the DT schema validator, the clkout child nodes are prescribed names clkout@[0-7] rather than clkout[0-7]. The example is refined as follows: - correct the usage of property pll-master -> silabs,pll-master - give an example of how the silabs,pll-reset property can be used I made myself maintainer of the file as I cannot presume that anybody else wants the responsibility. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-1-69b82311cb90@bang-olufsen.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17dt-bindings: stm32: add clocks and reset binding for stm32mp25 platformGabriel Fernandez
Adds clock and reset binding entries for STM32MP25 SoC family Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208143700.354785-4-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17dt-bindings: clk: rs9: Add 9FGV0841Marek Vasut
This is an 8-channel variant of 9FGV series. Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231113221949.111964-1-marek.vasut+renesas@mailbox.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17dt-bindings: clock: brcm,kona-ccu: convert to YAMLStanislav Jakubek
Convert Broadcom Kona family clock controller unit (CCU) bindings to DT schema. Changes during conversion: - remove "dmac" from clock-output-names for brcm,bcm11351-master-ccu, such a clock doesn't exist - remove "uartb4" from clock-output-names for brcm,bcm21664-slave-ccu, such a clock doesn't exist Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/ZVED01t3+coBd44x@standask-GA-A55M-S2HP Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17dt-bindings: arm: mediatek: move ethsys controller & convert to DT schemaRafał Miłecki
DT schema helps validating DTS files. Binding was moved to clock/ as this hardware is a clock provider. Example required a small fix for "reg" value (1 address cell + 1 size cell). Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2024-07-05 15:52:28 +0000