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The imx25, imx50, imx51 and imx53 SPIs are compatible with the imx35.
Document them accordingly.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230924183904.752415-1-festevam@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add support for generating DT nodes for PCI devices. This is the
groundwork for applying overlays to PCI devices containing
non-discoverable downstream devices.
- DT unittest additions to check reverted changesets, to test for
refcount issues, and to test unresolved symbols. Also, various
clean-ups of the unittest along the way.
- Refactor node and property manipulation functions to better share
code with old API and changeset API
- Refactor changeset print functions to a common implementation
- Move some platform_device specific functions into of_platform.c
Bindings:
- Treewide fixing of typos
- Treewide clean-up of SPDX tags to use 'OR' consistently
- Last chunk of dropping unnecessary quotes. With that, the check for
unnecessary quotes is enabled in yamllint.
- Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi
bindings to DT schema format
- Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450
Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt
controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings
- Fixes for Rockchip DWC PCI binding
- Ensure all properties are evaluated on USB connector schema
- Fix dt-check-compatible script to find of_device_id instances with
compiler annotations"
* tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits)
dt-bindings: usb: Add V3s compatible string for OHCI
dt-bindings: usb: Add V3s compatible string for EHCI
dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
dt-bindings: vendor-prefixes: document Saef Technology
dt-bindings: thermal: lmh: update maintainer address
of: unittest: Fix of_unittest_pci_node() kconfig dependencies
dt-bindings: crypto: ice: Document sm8450 inline crypto engine
dt-bindings: ufs: qcom: Add ICE to sm8450 example
dt-bindings: ufs: qcom: Add sm6115 binding
dt-bindings: ufs: qcom: Add reg-names property for ICE
dt-bindings: yamllint: Enable quoted string check
dt-bindings: Drop remaining unneeded quotes
of: unittest-data: Fix whitespace - angular brackets
of: unittest-data: Fix whitespace - indentation
of: unittest-data: Fix whitespace - blank lines
of: unittest-data: Convert remaining overlay DTS files to sugar syntax
of: overlay: unittest: Add test for unresolved symbol
of: unittest: Add separators to of_unittest_overlay_high_level()
of: unittest: Cleanup partially-applied overlays
of: unittest: Merge of_unittest_apply{,_revert}_overlay_check()
...
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Fix typos in Documentation/devicetree/bindings. The changes are in
descriptions or comments where they shouldn't affect functionality.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20230814212822.193684-3-helgaas@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
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Changes done during conversion:
* added a description, lifting and adapting the limitation sentence from
brcm,bcm63xx-hsspi.yml
* added appropriate compatibles for all SoCs that are supported by
bcm63xx/bmips
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://lore.kernel.org/r/20230727070806.12205-1-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The QSPI controller needs three clock items to work properly on StarFive
JH7110 SoC, so there is need to change the maxItems's value to 3.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230804020254.291239-2-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add a label property to allow a custom name to be used for identifying the
controller on a board. This is useful when there is more than one
controller present. Similar change was done by commit 412b7a521c30
("dt-bindings: eeprom: at24: Add label property for AT24").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/82cd1a57397867b5a1039cd15244344c02a3ece1.1691047461.git.michal.simek@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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ZynqMP Cadence SPI IP core has own power domain that's why describe it as
optional property.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/987430ee905fd299fe962663d94f848b341c87df.1691047461.git.michal.simek@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add the Loongson platform spi binding with DT schema format using
json-schema.
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230613075834.5219-2-zhuyinbo@loongson.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
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i.MX8(X) based SoC use a power domain. Allow supplying this domain in
bindings.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Acked-by: Han Xu <han.xu@nxp.com>
Link: https://lore.kernel.org/r/20230728060804.22796-1-alexander.stein@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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i.MX8(X) based SoC use a power domain. Allow supplying this domain in
bindings.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230721111020.1234278-2-alexander.stein@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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In JH7110 SoC, the spi module needs to use "arm,primecell-periphid" to
override the h/w ID value to correctly init "spi_dev", so add
"primecell.yaml" as the reference file for YAML.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230724101054.25268-2-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Convert the Tegra114 SPI controller device tree bindings from plain text
to json-schema format.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230705152603.2514235-3-thierry.reding@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Convert the Tegra SFLASH controller bindings from the free-form text
format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230705152603.2514235-2-thierry.reding@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Convert the Tegra SLINK bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230705152603.2514235-1-thierry.reding@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
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Commit a3eb95484f27 ("spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7
compatible") adding sam9x7 compatible did not make any sense as it added
new compatible into middle of existing compatible list. The intention
was probably to add new set of compatibles with sam9x7 as first one.
Fixes: a3eb95484f27 ("spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatible")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/Message-Id: <20230624082054.37697-1-krzysztof.kozlowski@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add sam9x7 compatible to DT bindings documentation.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Link: https://lore.kernel.org/r/Message-Id: <20230623203056.689705-33-varshini.rajendran@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add dt-bindings for the CSI IP found inside the RZ/V2M SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-2-fabrizio.castro.jz@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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STM32F4-F7 are, from hardware point of view, capable to handle device mode.
So this property should not be forced at false in dt-bindings.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/Message-Id: <20230621115523.923176-3-valentin.caron@foss.st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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STM32F4 and STM32F7 can't switch to spi device mode.
Forbid this property with compatible "st,stm32f4-spi".
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Link: https://lore.kernel.org/r/20230615075815.310261-4-valentin.caron@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Document the DesignWare SSI controller compatible for Intel Mount Evans
Integrated Management Complex SoC.
Signed-off-by: Abe Kohandel <abe.kohandel@intel.com>
Link: https://lore.kernel.org/r/20230606145402.474866-3-abe.kohandel@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
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Remove address/size-cells because they are already mentioned by common
spi-controller.yaml.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230601095908.563865-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Remove cs-gpios because it is already mentioned by common
spi-controller.yaml.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230601095908.563865-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Remove properties already mentioned by common spi-controller.yaml and
switch to unevaluatedProperties:false to achieve same functional effect.
This makes the binding a bit smaller. Similarly there is no need to
allow additionalProperties for children, because spi-controller.yaml
already does it.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230601095908.563865-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Make the pattern matching node names a bit stricter to improve DTS
consistency. The pattern is restricted to:
1. Only one unit address or one -N suffix,
2. -N suffixes to decimal numbers.
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230530144851.92059-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Document the cadence qspi controller compatible for AMD Pensando
Elba SoC boards. The Elba qspi fifo size is 1024.
Signed-off-by: Brad Larson <blarson@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230515181606.65953-3-blarson@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
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Listed above Allwinner SoCs has two SPI controllers. First is the regular
SPI controller and the second one has additional functionality for
MIPI-DBI Type C.
Add compatible strings for these controllers
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-2-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
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Merge series from Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>:
There are large number of QSPI irqs that fire during boot/init and later
on every suspend/resume.
This could be made faster by doing DMA instead of PIO.
Below is comparison for number of interrupts raised in 2 scenarios...
Boot up and stabilise
Suspend/Resume
Sequence PIO DMA
=======================
Boot-up 69088 19284
S/R 5066 3430
Speed test results...
spi-nor read times in sec after 2 min uptime
============================================
PIO - Iterations-1000, min=3.18, max=3.74, avg=3.53
DMA - Iterations-1000, min=1.21, max=2.28, avg=1.79
spi-nor write times in sec after 2 min uptime
=============================================
PIO - Iterations-1000, min=3.20, max=8.24, avg=3.58
DMA - Iterations-1000, min=1.25, max=5.13, avg=1.82
Further testing performed...
a) multiple entries in sgt (simulated by max_dma_len = 1024)
b) fallback to pio (simulated by dma setup failure)
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ZynqMP QSPI IP core has own power domain and also iommu ID that's why
describe optional power-domains and iommus properties.
Signed-off-by: Michal Simek <michal.simek@amd.com
Link: https://lore.kernel.org/r/2afed7285061abbb5d9ad3b1e795b737dcff9693.1683102032.git.michal.simek@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
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Add iommus binding for DMA mode support
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/1682328761-17517-2-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"A fairly standard release for SPI with the exception of a change to
the API for specifying chip selects done in preparation for supporting
devices with more than one chip select, this required some mechanical
changes throughout the tree which have been cooking in -next happily
for a while.
There's also a new API to allow us to support TPM chips on half duplex
controllers.
Summary:
- Refactoring in preparation for supporting multiple chip selects for
a single device, needed by some flash devices, which required a
change in the SPI device API visible throughout the tree
- Support for hardware assisted interaction with SPI TPMs on half
duplex controllers, implemented on nVidia Tedra210 QuadSPI
- Optimisation for large transfers on fsl-cpm devices
- Cleanups around device property use which fix some sisues with
fwnode
- Use of both void remove() and devm_platform_.*ioremap_resource()
- Support for AMD Pensando Elba, Amlogic A1, Cadence device mode,
Intel MetorLake-S and StarFive J7110 QuadSPI"
* tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (185 commits)
spi: bcm63xx: use macro DEFINE_SIMPLE_DEV_PM_OPS
spi: tegra210-quad: Enable TPM wait polling
spi: Add TPM HW flow flag
spi: bcm63xx: remove PM_SLEEP based conditional compilation
spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS
spi: spi-cadence: Add support for Slave mode
spi: spi-cadence: Switch to spi_controller structure
spi: cadence-quadspi: fix suspend-resume implementations
spi: dw: Add support for AMD Pensando Elba SoC
spi: dw: Add AMD Pensando Elba SoC SPI Controller
spi: cadence-quadspi: Disable the SPI before reconfiguring
spi: cadence-quadspi: Update the read timeout based on the length
spi: spi-loopback-test: Add module param for iteration length
spi: add support for Amlogic A1 SPI Flash Controller
dt-bindings: spi: add Amlogic A1 SPI controller
spi: fsl-spi: No need to check transfer length versus word size
spi: fsl-spi: Change mspi_apply_cpu_mode_quirks() to void
spi: fsl-cpm: Use 16 bit mode for large transfers with even size
spi: fsl-spi: Re-organise transfer bits_per_word adaptation
spi: fsl-spi: Fix CPM/QE mode Litte Endian
...
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The AMD Pensando Elba SoC has integrated the DW APB SPI Controller
Signed-off-by: Brad Larson <blarson@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20230410184526.15990-5-blarson@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add YAML devicetree Amlogic A1 (A113L SoC) SPIFC.
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230403183217.13280-2-mmkurbanov@sberdevices.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
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schemas
Just as unevaluatedProperties or additionalProperties are required at
the top level of schemas, they should (and will) also be required for
child node schemas. That ensures only documented properties are
present.
Add unevaluatedProperties or additionalProperties as appropriate, and
then add any missing properties flagged by the addition.
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Lee Jones <lee@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230124230228.372305-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
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Make "clocks" and "power-domains" required everywhere.
Make "resets" required on R-Car Gen2 and newer (i.e. all but SH-Mobile).
Update the example to match reality:
- Use interrupt binding definitions instead of hardcoded numbers,
- Convert to new-style CPG/MSSR bindings,
- Add missing "power-domains" and "resets" properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/052af97ecbaa9ba6e0d406883dd3389fa397579a.1678891999.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
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Enable yamllint to check the preferred commenting style of requiring a
space after a comment character '#'. Fix the cases in the tree which
have a warning with this enabled. Most cases just need a space after the
'#'. A couple of cases with comments which were not intended to be
comments are revealed. Those were in ti,sa2ul.yaml, ti,cal.yaml, and
brcm,bcmgenet.yaml.
Acked-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # drm/msm
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230303214223.49451-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
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The QSPI controller needs three reset items to work properly on JH7110 SoC,
so there is need to change the maxItems's value to 3 and add minItems
whose value is equal to 2. Other platforms do not have this constraint.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-2-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"This has been a fairly quiet release for SPI, though it is likely that
the next release will have some big changes as there's some
preparatory work for multiple chip select support gone in - the rest
of the code is on the list but will need to be rebased onto -rc1.
Otherwise there's a couple of new tunables for chip select timings,
some new devices and smaller device specific updates and fixes.
- Support for configuring the hold and minimum inactive times for
chip selects.
- Beginnings of support for supporting devices which have multiple
chip selects on a single device.
- Support for newer Broadcom HSSPI and Intel controllers, Silicon
Labs EM3581 and SI3210"
* tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits)
spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains
spi: spidev: drop the incorrect notice from Kconfig
spi: bcm63xx-hsspi: fix error code in probe
spi: bcmbca-hsspi: Fix error code in probe() function
spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one()
spi: intel: Check number of chip selects after reading the descriptor
spi: xilinx: add force_irq for QSPI mode
spi: spi-st-ssc: convert to DT schema
spi: Reorder fields in 'struct spi_transfer'
spi: cadence-quadspi: use STIG mode for small reads
spi: cadence-quadspi: setup ADDR Bits in cmd reads
spi: cadence-quadspi: Add flag for direct mode writes
spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry
spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage
MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers
spi: bcmbca-hsspi: Add driver for newer HSSPI controller
spi: bcm63xx-hsspi: Disable spi mem dual io read op support
spi: spi-mem: Allow controller supporting mem_ops without exec_op
spi: bcm63xx-hsspi: Add prepend mode support
...
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QSPI on Qualcomm SDM845, SC7180 and SC7280 SoCs uses OPP table (both in
DTS and Linux driver) and is suuplied by CX power domain. Document
missing properties to fix:
sc7280-idp2.dtb: spi@88dc000: Unevaluated properties are not allowed ('operating-points-v2', 'power-domains' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230217155802.848178-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Convert spi-st-ssc.txt into st,ssc-spi.yaml for the
ST Microelectronics SSC SPI driver.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230213192349.17101-1-avolmat@me.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Xiangsheng Hou <xiangsheng.hou@mediatek.com>:
This patch series split from bellow series which pick-up spi relevant patches
https://lore.kernel.org/all/20230130030656.12127-1-xiangsheng.hou@mediatek.com.
This series add MediaTek MT7986 SPI NAND controller support, add read latch
latency, smaple delay adjust and add optional nfi_hclk.
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Add mediatek,rx-latch-latency-ns property which adjust data read
latch latency in the unit of nanoseconds.
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230201020921.26712-6-xiangsheng.hou@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add dt-bindings documentation of SPI NAND controller
for MediaTek MT7986 SoC platform. And add optional
nfi_hclk property which is needed for MT7986.
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230201020921.26712-4-xiangsheng.hou@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The new Broadcom Broadband BCMBCA SoCs includes a updated HSSPI
controller. Add new compatible strings to differentiate the old and new
controller while keeping MIPS based chip with the old compatible. Update
property requirements for these two revisions of the controller. Also
add myself and Kursad as the maintainers.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230207065826.285013-3-william.zhang@broadcom.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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This is the preparation for updates on the bcm63xx hsspi driver. Convert
the text based bindings to json-schema per new dts requirement.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230207065826.285013-2-william.zhang@broadcom.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Cleanup examples:
- use 4-space indentation (for cases when it is neither 4 not 2 space),
- drop redundant blank lines,
- use lowercase hex.
No functional impact except adjusting to preferred coding style.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Reviewed-by: Andrew Jeffery <andrew@aj.id.au> # aspeed
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> # meson
Link: https://lore.kernel.org/r/20230124083342.34869-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Cleanup by removing unneeded quotes from refs and redundant blank lines.
No functional impact except adjusting to preferred coding style.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au> # aspeed
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> # meson
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # st
Reviewed-by: Heiko Stuebner <heiko@sntech.de> # rockchip
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # synopsys
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230124083342.34869-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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These two properties complete the bindings for the Linux spi_device cs
model, which includes cs_setup, cs_hold and cs_inactive delay values.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20230113102309.18308-3-marcan@marcan.st
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
- Fixes for long standing issues with accesses to spidev->spi during
teardown in the spidev userspace driver.
- Rename the newly added spi-cs-setup-ns DT property to be more in line
with our other delay properties before it becomes ABI.
- A few driver specific fixes.
* tag 'spi-fix-v6.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spidev: remove debug messages that access spidev->spi without locking
spi: spidev: fix a race condition when accessing spidev->spi
spi: Rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
spi: dt-bindings: Rename spi-cs-setup-ns to spi-cs-setup-delay-ns
spi: cadence: Fix busy cycles calculation
spi: mediatek: Enable irq before the spi registration
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