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2024-03-05spi: dt-bindings: introduce FIFO depth propertiesTudor Ambarus
There are SPI IPs that can be configured by the integrator with a specific FIFO depth depending on the system's capabilities. For example, the samsung USI SPI IP can be configured by the integrator with a TX/RX FIFO from 8 byte to 256 bytes. Introduce the ``fifo-depth`` property for such instances of IPs where the same FIFO depth is used for both RX and TX. Introduce ``rx-fifo-depth`` and ``tx-fifo-depth`` properties for cases where the RX FIFO depth is different from the TX FIFO depth. Make the dedicated RX/TX properties dependent on each other and mutual exclusive with the other. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240216070555.2483977-2-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-03-04spi: dt-bindings: samsung: make dma properties not requiredTudor Ambarus
Since the addition of the driver in 2009, the driver selects between DMA and polling mode depending on the transfer length - DMA mode for transfers bigger than the FIFO depth, polling mode otherwise. All versions of the IP support polling mode, make the dma properties not required. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://msgid.link/r/20240301115546.2266676-1-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-28spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from listVarshini Rajendran
Remove microchip,sam9x60-spi compatible from the list as the driver used has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the same compatible as fallback. So removing the microchip,sam9x60-spi compatible from the list since it is not needed. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://msgid.link/r/20240223172638.672366-1-varshini.rajendran@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-08spi: dt-bindings: samsung: add google,gs101-spi compatibleTudor Ambarus
Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240207111516.2563218-2-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-24spi: dt-bindings: samsung: Add Exynos850 SPISam Protsenko
Document samsung,exynos850-spi compatible which will be used on Exynos850 SoC. Exynos850 doesn't have ioclk, so only two clocks are needed (bus clock and functional SPI clock). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20240120012948.8836-3-semen.protsenko@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-22dt-bindings: spi: nxp-fspi: support i.MX93 and i.MX95Peng Fan
Add i.MX93/95 flexspi compatible strings, which are compatible with i.MX8MM Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240122091510.2077498-2-peng.fan@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-22dt-bindings: spi: fsl-lpspi: support i.MX95 LPSPIPeng Fan
Add i.MX95 LPSPI compatible string, same as i.MX93 compatible with i.MX7ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240122091510.2077498-1-peng.fan@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-12-21dt-bindings: spi: stm32: add st,stm32mp25-spi compatibleValentin Caron
Add st,stm32mp25-spi compatible in dt-bindings. STM32MP25 spi is similar to the STM32H7 except for the following two points: - Burst should not be enabled with the new DMA used on STM32MP25. - STM32MP25 SPI8 has a limited feature set, it can only send words of 8 or 16 bits and with a maximum words number of 1024. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20231218155721.359198-3-alain.volmat@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-12-13spi: dw: Remove Intel Thunder Bay SOC supportNandhini Srikandan
Remove Intel Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20231213060836.29203-3-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-11-20spi: axi-spi-engine improvementsMark Brown
Merge series from David Lechner <dlechner@baylibre.com>: We are working towards adding support for the offload feature[1] of the AXI SPI Engine IP core. Before we can do that, we want to make some general fixes and improvements to the driver. In order to avoid a giant series with 35+ patches, we are splitting this up into a few smaller series. This first series mostly doing some housekeeping: * Convert device tree bindings to yaml. * Add a MAINTAINERS entry. * Clean up probe and remove using devm. * Separate message state from driver state. * Add support for cs_off and variable word size. Once this series is applied, we will follow up with a second series of general improvements, and then finally a 3rd series that implements the offload support. The offload support will also involve the IIO subsystem (a new IIO driver will depend on the new SPI offload feature), so I'm mentioning this now in case we want to do anything ahead of time to prepare for that (e.g. putting all of these changes on a separate branch). [1]: https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload
2023-11-20dt-bindings: spi: axi-spi-engine: convert to yamlDavid Lechner
This converts the axi-spi-engine binding to yaml. There are a few minor fixes in the conversion: * Added maintainers. * Added descriptions for the clocks. * Fixed the double "@" in the example. * Added a comma between the clocks in the example. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231117-axi-spi-engine-series-1-v1-1-cc59db999b87@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-11-16spi: dt-bindings: renesas,rspi: Document RZ/Five SoCLad Prabhakar
The RSPI block on the RZ/Five SoC is identical to one found on the RZ/G2UL SoC. "renesas,r9a07g043-rspi" compatible string will be used on the RZ/Five SoC so to make this clear and to keep this file consistent, update the comment to include RZ/Five SoC. No driver changes are required as generic compatible string "renesas,rspi-rz" will be used as a fallback on RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231115205333.31076-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-11-13spi: add stm32f7-spi compatibleBen Wolsieffer
The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the only significant differences being support for a wider range of word sizes and the addition of 32-bit transmit and receive FIFOs. Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231102193722.3042245-4-ben.wolsieffer@hefring.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-10-30spi: Merge up fixMark Brown
One small fix that didn't seem worth sending before the merge window.
2023-10-09spi: renesas,rzv2m-csi: Add CSI (SPI) target related propertyFabrizio Castro
The CSI IP found inside the Renesas RZ/V2M SoC can also work in SPI target mode. When working in target mode, the IP will make use of the SS (Slave Selection) pin, with "low" as default active level. The active level of SS can be changed to "high" upon setting property "spi-cs-high" to true. By default, the SS will be used in target mode, unless property "renesas,csi-no-ss" is set to true, in which case data will be shifted in and out purely based on clock activity, and the logic level of the SS pin will be completely ignored. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230927162508.328736-2-fabrizio.castro.jz@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-26spi: dt-bindings: Make "additionalProperties: true" explicitRob Herring
Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230925212614.1974243-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-26spi: qup: Allow scaling power domains andMark Brown
Merge series from Stephan Gerhold <stephan.gerhold@kernkonzept.com>: Make it possible to scale performance states of the power domain and interconnect of the SPI QUP controller in relation to the selected SPI speed / core clock. This is done separately by: - Parsing the OPP table from the device tree for performance state votes of the power domain - Voting for the necessary bandwidth on the interconnect path to DRAM
2023-09-25spi: dt-bindings: st,stm32-spi: Move "st,spi-midi-ns" to ↵Rob Herring
spi-peripheral-props.yaml In order to validate SPI peripherals, SPI controller-specific child node properties need to be in a separate schema, spi-peripheral-props.yaml, which SPI peripheral schemas reference. As there is just a single property in this case, just add it to spi-peripheral-props.yaml directly. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230914190049.1853136-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-25spi: dt-bindings: qup: Document interconnectsStephan Gerhold
When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Link: https://lore.kernel.org/r/20230919-spi-qup-dvfs-v2-3-1bac2e9ab8db@kernkonzept.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-25spi: dt-bindings: qup: Document power-domains and OPPStephan Gerhold
Document power-domains and operating-points-v2 to allow making performance state votes for certain clock frequencies of the SPI QUP controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Link: https://lore.kernel.org/r/20230919-spi-qup-dvfs-v2-1-1bac2e9ab8db@kernkonzept.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-25dt-bindings: spi: fsl-imx-cspi: Document missing entriesFabio Estevam
The imx25, imx50, imx51 and imx53 SPIs are compatible with the imx35. Document them accordingly. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230924183904.752415-1-festevam@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-15spi: dt-bindings: arm,pl022: Move child node properties to separate schemaRob Herring
In order to validate SPI peripherals, SPI controller-specific child node properties need to be in a separate schema, spi-peripheral-props.yaml, which SPI peripheral schemas reference. Move the arm,pl022 child properties to their own schema file and add a $ref in spi-peripheral-props.yaml. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230914190033.1852600-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-30Merge tag 'devicetree-for-6.6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add support for generating DT nodes for PCI devices. This is the groundwork for applying overlays to PCI devices containing non-discoverable downstream devices. - DT unittest additions to check reverted changesets, to test for refcount issues, and to test unresolved symbols. Also, various clean-ups of the unittest along the way. - Refactor node and property manipulation functions to better share code with old API and changeset API - Refactor changeset print functions to a common implementation - Move some platform_device specific functions into of_platform.c Bindings: - Treewide fixing of typos - Treewide clean-up of SPDX tags to use 'OR' consistently - Last chunk of dropping unnecessary quotes. With that, the check for unnecessary quotes is enabled in yamllint. - Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi bindings to DT schema format - Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450 Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings - Fixes for Rockchip DWC PCI binding - Ensure all properties are evaluated on USB connector schema - Fix dt-check-compatible script to find of_device_id instances with compiler annotations" * tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits) dt-bindings: usb: Add V3s compatible string for OHCI dt-bindings: usb: Add V3s compatible string for EHCI dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B dt-bindings: vendor-prefixes: document Saef Technology dt-bindings: thermal: lmh: update maintainer address of: unittest: Fix of_unittest_pci_node() kconfig dependencies dt-bindings: crypto: ice: Document sm8450 inline crypto engine dt-bindings: ufs: qcom: Add ICE to sm8450 example dt-bindings: ufs: qcom: Add sm6115 binding dt-bindings: ufs: qcom: Add reg-names property for ICE dt-bindings: yamllint: Enable quoted string check dt-bindings: Drop remaining unneeded quotes of: unittest-data: Fix whitespace - angular brackets of: unittest-data: Fix whitespace - indentation of: unittest-data: Fix whitespace - blank lines of: unittest-data: Convert remaining overlay DTS files to sugar syntax of: overlay: unittest: Add test for unresolved symbol of: unittest: Add separators to of_unittest_overlay_high_level() of: unittest: Cleanup partially-applied overlays of: unittest: Merge of_unittest_apply{,_revert}_overlay_check() ...
2023-08-18dt-bindings: Fix typosBjorn Helgaas
Fix typos in Documentation/devicetree/bindings. The changes are in descriptions or comments where they shouldn't affect functionality. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20230814212822.193684-3-helgaas@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-08-07dt-bindings: spi: convert spi-brcm63xx.txt to YAMLJonas Gorski
Changes done during conversion: * added a description, lifting and adapting the limitation sentence from brcm,bcm63xx-hsspi.yml * added appropriate compatibles for all SoCs that are supported by bcm63xx/bmips Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Link: https://lore.kernel.org/r/20230727070806.12205-1-jonas.gorski@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-04dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoCWilliam Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230804020254.291239-2-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-03dt-bindings: spi: spi-cadence: Add label propertyMichal Simek
Add a label property to allow a custom name to be used for identifying the controller on a board. This is useful when there is more than one controller present. Similar change was done by commit 412b7a521c30 ("dt-bindings: eeprom: at24: Add label property for AT24"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/82cd1a57397867b5a1039cd15244344c02a3ece1.1691047461.git.michal.simek@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-03dt-bindings: spi: spi-cadence: Describe power-domains propertyMichal Simek
ZynqMP Cadence SPI IP core has own power domain that's why describe it as optional property. Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/987430ee905fd299fe962663d94f848b341c87df.1691047461.git.michal.simek@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-31spi: dt-bindings: add loongson spiYinbo Zhu
Add the Loongson platform spi binding with DT schema format using json-schema. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230613075834.5219-2-zhuyinbo@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-28spi: fspi: Add power-domains to the DT bindingsAlexander Stein
i.MX8(X) based SoC use a power domain. Allow supplying this domain in bindings. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/20230728060804.22796-1-alexander.stein@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-24spi: lpspi: Add power-domains to the DT bindingsAlexander Stein
i.MX8(X) based SoC use a power domain. Allow supplying this domain in bindings. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230721111020.1234278-2-alexander.stein@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-24dt-bindings: spi: add reference file to YAMLWilliam Qiu
In JH7110 SoC, the spi module needs to use "arm,primecell-periphid" to override the h/w ID value to correctly init "spi_dev", so add "primecell.yaml" as the reference file for YAML. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230724101054.25268-2-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-09dt-bindings: spi: Convert Tegra114 SPI to json-schemaThierry Reding
Convert the Tegra114 SPI controller device tree bindings from plain text to json-schema format. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230705152603.2514235-3-thierry.reding@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-09dt-bindings: spi: tegra-sflash: Convert to json-schemaThierry Reding
Convert the Tegra SFLASH controller bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230705152603.2514235-2-thierry.reding@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-09dt-bindings: spi: tegra-slink: Convert to json-schemaThierry Reding
Convert the Tegra SLINK bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230705152603.2514235-1-thierry.reding@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-06-24spi: dt-bindings: atmel,at91rm9200-spi: fix broken sam9x7 compatibleKrzysztof Kozlowski
Commit a3eb95484f27 ("spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatible") adding sam9x7 compatible did not make any sense as it added new compatible into middle of existing compatible list. The intention was probably to add new set of compatibles with sam9x7 as first one. Fixes: a3eb95484f27 ("spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatible") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/Message-Id: <20230624082054.37697-1-krzysztof.kozlowski@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-23spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatibleVarshini Rajendran
Add sam9x7 compatible to DT bindings documentation. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Link: https://lore.kernel.org/r/Message-Id: <20230623203056.689705-33-varshini.rajendran@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-23spi: dt-bindings: Add bindings for RZ/V2M CSIFabrizio Castro
Add dt-bindings for the CSI IP found inside the RZ/V2M SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-2-fabrizio.castro.jz@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-22spi: dt-bindings: stm32: do not disable spi-slave property for stm32f4-f7Valentin Caron
STM32F4-F7 are, from hardware point of view, capable to handle device mode. So this property should not be forced at false in dt-bindings. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/Message-Id: <20230621115523.923176-3-valentin.caron@foss.st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-15spi: stm32: disable spi-slave property for stm32f4-f7Alain Volmat
STM32F4 and STM32F7 can't switch to spi device mode. Forbid this property with compatible "st,stm32f4-spi". Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20230615075815.310261-4-valentin.caron@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-06spi: dt-bindings: snps,dw-apb-ssi: Add compatible for Intel Mount Evans SoCAbe Kohandel
Document the DesignWare SSI controller compatible for Intel Mount Evans Integrated Management Complex SoC. Signed-off-by: Abe Kohandel <abe.kohandel@intel.com> Link: https://lore.kernel.org/r/20230606145402.474866-3-abe.kohandel@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-05dt-bindings: xilinx: Switch xilinx.com emails to amd.comMichal Simek
@xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
2023-06-01spi: dt-bindings: socionext,uniphier: drop address/size-cellsKrzysztof Kozlowski
Remove address/size-cells because they are already mentioned by common spi-controller.yaml. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230601095908.563865-3-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-01spi: dt-bindings: samsung: drop cs-gpiosKrzysztof Kozlowski
Remove cs-gpios because it is already mentioned by common spi-controller.yaml. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230601095908.563865-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-01spi: dt-bindings: allwinner: simplify with unevaluatedPropertiesKrzysztof Kozlowski
Remove properties already mentioned by common spi-controller.yaml and switch to unevaluatedProperties:false to achieve same functional effect. This makes the binding a bit smaller. Similarly there is no need to allow additionalProperties for children, because spi-controller.yaml already does it. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230601095908.563865-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-05-30spi: dt-bindings: restrict node name suffixesKrzysztof Kozlowski
Make the pattern matching node names a bit stricter to improve DTS consistency. The pattern is restricted to: 1. Only one unit address or one -N suffix, 2. -N suffixes to decimal numbers. Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230530144851.92059-6-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-05-17spi: cdns: Add compatible for AMD Pensando Elba SoCBrad Larson
Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson <blarson@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230515181606.65953-3-blarson@amd.com Signed-off-by: Mark Brown <broonie@kernel.org
2023-05-12spi: sun6i: add DT bindings for Allwinner R329/D1/R528/T113s SPIMaksim Kiselev
Listed above Allwinner SoCs has two SPI controllers. First is the regular SPI controller and the second one has additional functionality for MIPI-DBI Type C. Add compatible strings for these controllers Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org Reviewed-by: Andre Przywara <andre.przywara@arm.com Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com Link: https://lore.kernel.org/r/20230510081121.3463710-2-bigunclemax@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org
2023-05-08spi: Add DMA mode support to spi-qcom-qspiMark Brown
Merge series from Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>: There are large number of QSPI irqs that fire during boot/init and later on every suspend/resume. This could be made faster by doing DMA instead of PIO. Below is comparison for number of interrupts raised in 2 scenarios... Boot up and stabilise Suspend/Resume Sequence PIO DMA ======================= Boot-up 69088 19284 S/R 5066 3430 Speed test results... spi-nor read times in sec after 2 min uptime ============================================ PIO - Iterations-1000, min=3.18, max=3.74, avg=3.53 DMA - Iterations-1000, min=1.21, max=2.28, avg=1.79 spi-nor write times in sec after 2 min uptime ============================================= PIO - Iterations-1000, min=3.20, max=8.24, avg=3.58 DMA - Iterations-1000, min=1.25, max=5.13, avg=1.82 Further testing performed... a) multiple entries in sgt (simulated by max_dma_len = 1024) b) fallback to pio (simulated by dma setup failure)
generated by cgit (git 2.34.1) at 2024-06-14 07:55:09 +0000