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2024-11-06spi: dt-bindings: apple,spi: Add binding for Apple SPI controllersHector Martin
The Apple SPI controller is present in SoCs such as the M1 (t8103) and M1 Pro/Max (t600x). This controller uses one IRQ and one clock, and doesn't need any special properties, so the binding is trivial. Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Nick Chan <towinchenmi@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Link: https://patch.msgid.link/20241106-asahi-spi-v5-1-e81a4f3a8e19@jannau.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-31dt-bindings: spi: sprd,sc9860-spi: convert to YAMLStanislav Jakubek
Convert the Spreadtrum SC9860 SPI controller bindings to DT schema. Adjust filename to match compatible. Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/ZyH2P3FlneLtGxXo@standask-GA-A55M-S2HP Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-21Realtek SPI-NAND controllerMark Brown
Merge series from Chris Packham <chris.packham@alliedtelesis.co.nz>: This series adds support for the SPI-NAND flash controller on the RTL9300 family of SoCs. There are 2 physical chip selects which are called SPI_MST_CS0 and SPI_MST_CS1 in the datasheet. Via some pin-strapping these can be assigned to either the SPI-NOR controller or the SPI-NAND controller. Which means you can end up with the following permutations SPI-Flash Boot Model SPI_MST_CS0 SPI_MST_CS1 ---------- ----------- ----------- NOR x1 NOR-CS0 X NOR x2 NOR-CS0 NOR-CS1 NAND x1 NAND-CS0 X NAND x2 NAND-CS0 NAND-CS1 NOR+NAND NOR-CS0 NAND-CS0
2024-10-21spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spiIvaylo Ivanov
According to the vendor kernel, the Exynos8895 SoC has an SPI configuration that matches with the Exynos850 one. SPI FIFO depth is 64 bytes for all SPI blocks. All blocks have DIV_4 as the default internal clock divider, and an internal loopback mode to run a loopback test. Reuse the samsung,exynos850-spi compatible. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20241020182121.377969-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-21dt-bindings: spi: Add realtek,rtl9301-snandChris Packham
Add a dtschema for the SPI-NAND controller on the RTL9300 SoCs. The controller supports * Serial/Dual/Quad data with * PIO and DMA data read/write operation * Configurable flash access timing Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20241015225434.3970360-2-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-17spi: dt-bindings: brcm,bcm2835-aux-spi: Convert to dtschemaKaran Sanghavi
Convert bcm2835-aux-spi binding to Dt schema Signed-off-by: Karan Sanghavi <karansanghvi98@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/ZxEm-H-PjlQyXeOH@Emma Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the ↵Amit Kumar Mahapatra
Zynq UltraScale QSPI Linear mode is only supported by the Zynq UltraScale QSPI controller, so update the bindings to include two 'reg' properties only for the Zynq UltraScale QSPI controller. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20240925114203.2234735-1-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-26Merge tag 'soc-ep93xx-dt-6.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...
2024-09-12dt-bindings: spi: Add Cirrus EP93xxNikita Shubin
Add YAML bindings for ep93xx SoC SPI. Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05dt-bindings: spi: nxp-fspi: add imx8ulp supportHaibo Chen
The flexspi on imx8ulp only has 16 number of LUTs, it is different with flexspi on other imx SoC which has 32 number of LUTs. Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node") Cc: stable@kernel.org Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240905094338.1986871-2-haibo.chen@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-03spi: dt-bindings: Add rockchip,rk3576-spi compatibleDetlev Casanova
It is compatible with the rockchip,rk3066-spi SPI core. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20240903152308.13565-8-detlev.casanova@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-14dt-bindings: spi: add PIC64GX SPI/QSPI compatibility to MPFS SPI/QSPI bindingsPierre-Henry Moussay
PIC64GX SPI/QSPI are compatible with MPFS SPI/QSPI driver, we just use fallback mechanism Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Link: https://patch.msgid.link/20240725121609.13101-5-pierre-henry.moussay@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-13spi: dt-bindings: convert spi-sc18is602.txt to yaml formatFrank Li
Convert binding doc spi-sc18is602.txt (I2C to SPI bridge) to yaml. Additional change: - ref spi-controller.yaml Fix below warning: arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dtb: /soc/i2c@2000000/i2c-mux@77/i2c@7/i2c-mux@75/i2c@0/spi@28: failed to match any schema with compatible: ['nxp,sc18is602b'] Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240813154444.3886690-1-Frank.Li@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-29Marvell HW overlay support for Cadence xSPIMark Brown
Merge series from Witold Sadowski <wsadowski@marvell.com>: This patch series adds support for the second version of the Marvell hardware overlay for the Cadence xSPI IP block. The overlay is a hardware change made around the original xSPI block. It extends xSPI features with clock configuration, interrupt masking, and full-duplex, variable-length SPI operations. These functionalities allow the xSPI block to operate not only with memory devices but also with simple SPI devices and TPM devices. Example ACPI entry: Device (SPI0) { Name (_HID, "PRP0001") // ACPI_DT_NAMESPACE_HID Name (_UID, 0) Name (_DDN, "SPI controller 0") Name (_CCA, ONE) Method (_STA) {Return (0xF)} Name (_CRS, ResourceTemplate() { QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000000000, // MinAddress 0x804000001037, // MaxAddress 0, // AddressTranslation 0x1038) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804010000000, // MinAddress 0x804010000007, // MaxAddress 0, // AddressTranslation 0x8) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000002000, // MinAddress 0x804000004027, // MaxAddress 0, // AddressTranslation 0x2028) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000008000, // MinAddress 0x804000008237, // MaxAddress 0, // AddressTranslation 0x238) // AddressLength Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) { 0x7A } }) Name (_DSD, Package() { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "compatible", "marvell,cn10-xspi-nor"}, Package () { "reg", 0x8040}, } }) } // SPI0
2024-07-29spi: dt-bindings: mediatek,spi-mt65xx: add compatible for MT7981Rafał Miłecki
MT7981 has SPI controllers based on IPM design Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20240727114828.29558-1-zajec5@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-29spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for ↵Witold Sadowski
Cadence XSPI Add new bindings for the v2 Marvell xSPI overlay: marvell,cn10-xspi-nor compatible string. This new compatible string distinguishes between the original and modified xSPI block. Also add an optional base for the xfer register set with an additional reg field to allocate the xSPI Marvell overlay XFER block. Signed-off-by: Witold Sadowski <wsadowski@marvell.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20240724154739.582367-2-wsadowski@marvell.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-24Merge tag 'dmaengine-6.11-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "New support: - New dmaengine_prep_peripheral_dma_vec() to support transfers using dma vectors and documentation and user in AXI dma - STMicro STM32 DMA3 support and new capabilities of cyclic dma Updates: - Yaml conversion for Freescale imx dma and qdma bindings, sprd sc9860 dma binding - Altera msgdma updates for descriptor management" * tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits) dt-bindings: fsl-qdma: fix interrupts 'if' check logic dt-bindings: dma: sprd,sc9860-dma: convert to YAML dmaengine: fsl-dpaa2-qdma: add missing MODULE_DESCRIPTION() macro dmaengine: ti: add missing MODULE_DESCRIPTION() macros dmaengine: ti: cppi41: add missing MODULE_DESCRIPTION() macro dmaengine: virt-dma: add missing MODULE_DESCRIPTION() macro dmaengine: ti: k3-udma: Fix BCHAN count with UHC and HC channels dmaengine: sh: rz-dmac: Fix lockdep assert warning dmaengine: qcom: gpi: clean up the IRQ disable/enable in gpi_reset_chan() dmaengine: fsl-edma: change the memory access from local into remote mode in i.MX 8QM dmaengine: qcom: gpi: remove unused struct 'reg_info' dmaengine: moxart-dma: remove unused struct 'moxart_filter_data' dt-bindings: fsl-qdma: Convert to yaml format dmaengine: fsl-edma: remove redundant "idle" field from fsl_chan dmaengine: fsl-edma: request per-channel IRQ only when channel is allocated dmaengine: stm32-dma3: defer channel registration to specify channel name dmaengine: add channel device name to channel registration dmaengine: stm32-dma3: improve residue granularity dmaengine: stm32-dma3: add device_pause and device_resume ops dmaengine: stm32-dma3: add DMA_MEMCPY capability ...
2024-07-17Merge tag 'devicetree-for-6.11' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT Bindings: - Convert and add a bunch of IBM FSI related bindings - Add a new schema listing legacy compatibles which will (probably) never be documented. This will silence various checks warning about them. - Add bindings for Sierra Wireless mangOH Green SPI IoT interface, new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75 GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and CSI-2 blocks - Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema - Drop obsolete stericsson,abx500.txt DT core: - Update dtc to upstream version v1.7.0-93-g1df7b047fe43 - Add support to run DT validation on DTs with applied overlays - Add helper for creating boolean properties in dynamic nodes and use that for dynamic PCI nodes - Clean-up early parsing of '#{address,size}-cells'" * tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits) dt-bindings: timer: sprd-timer: convert to YAML dt-bindings: incomplete-devices: document devices without bindings dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43 dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node dt-bindings: soc: fsl: cpm_qe: convert to yaml format dt-bindings: i2c: i2c-fsi: Convert to json-schema dt-bindings: fsi: Document the FSI Hub Controller dt-bindings: fsi: Document the AST2700 FSI controller dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller dt-bindings: fsi: Document the FSI controller common properties dt-bindings: fsi: Document the IBM SBEFIFO engine dt-bindings: fsi: p9-occ: Convert to json-schema dt-bindings: fsi: Document the IBM SCOM engine dt-bindings: fsi: fsi2spi: Document SPI controller child nodes dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml dt-bindings: soc: fsl: Convert q(b)man-* to yaml format dt-bindings: misc: fsl,qoriq-mc: convert to yaml format dt-bindings: drop stale Anson Huang from maintainers ...
2024-07-12spi: dt-bindings: at91: Add sama7d65 compatible stringNicolas Ferre
Add compatible string for sama7d65. Like sam9x60 and sam9x7, it requires to bind to "atmel,at91rm9200-spi". Group these three under the same enum, sorted alphanumerically, and remove previously added item. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20240711165402.373634-1-nicolas.ferre@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-09dt-bindings: drop stale Anson Huang from maintainersKrzysztof Kozlowski
Emails to Anson Huang bounce: Diagnostic-Code: smtp; 550 5.4.1 Recipient address rejected: Access denied. Add IMX platform maintainers for bindings which would become orphaned. Acked-by: Uwe Kleine-König <ukleinek@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # for I2C Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # for IIO Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240617065828.9531-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-07-08spi: dt-bindings: fsl-dspi: add compatible string 'fsl,lx2160a-dspi'Frank Li
Add compatible string 'fsl,lx2160a-dspi' and allow fall back to 'fsl,ls2085a-dspi'. Fix below CHECK_DTBS warning. arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dtb: spi@2100000: compatible: 'oneOf' conditional failed, one must be fixed: ['fsl,lx2160a-dspi', 'fsl,ls2085a-dspi'] is too long Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240703165931.2325807-2-Frank.Li@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-08spi: dt-bindings: fsl-dspi: add dmas and dma-names propertiesFrank Li
Add dmas and dma-names properties because dspi support dma transfer. Fix below warnings: arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb: spi@2120000: Unevaluated properties are not allowed ('dma-names', 'dmas', 'little-endian' were unexpected) from schema $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml# Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Link: https://patch.msgid.link/20240703165931.2325807-1-Frank.Li@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-01spi: dt-bindings: snps,dw-apb-ssi.yaml: update compatible propertyKanak Shilledar
updated compatible property to include "thead,th1520-spi" for the TH1520 SoC SPI Controller. Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20240701121355.262259-3-kanakshilledar@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-01spi: dt-bindings: fsl-dspi: Convert to yaml formatFrank Li
Convert dt-binding spi-fsl-dspi.txt to yaml format. Use part Vladimir Oltean's work at of https://lore.kernel.org/linux-spi/20221111224651.577729-1-vladimir.oltean@nxp.com/ Additional changes during convert: - compatible string "fsl,ls1028a-dspi" can be followed by fsl,ls1021a-v1.0-dspi. - Change "dspi0@4002c000" to "spi@4002c000" in example. - Reorder properties in example. - Use GIC include in example. - Deprecated fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay by use common SPI property. - Use compatible string 'jedec,spi-nor' in example. - Split peripheral part to fsl,dspi-peripheral-props.yaml. - Remove 'interrupts' and 'pinctrl' from required list. - Update 'bus-num' description. - Update 'spi-num-chipselects' description by add "cs-gpios don't count against this number". - Remove 'big-endian' description. Co-developed-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Co-developed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20240624-ls_qspi-v4-2-3d1c6f5005bf@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-06-11dt-bindings: dma: New directory for STM32 DMA controllers bindingsAmelie Delaunay
Gather the STM32 DMA controllers bindings under ./dma/stm32/. Then fix reference to old path in spi/st,stm32-spi.yaml: update the dmas property description by referring to all STM32 DMA controllers bindings. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20240531150712.2503554-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-05dt-bindings: spi: amlogic,a1-spifc: add missing power-domainsNeil Armstrong
On the Amlogic A1, the SPI FC controller can require a power-domain to operate, add it as optional. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240605-topic-amlogic-upstream-bindings-fixes-power-domains-spifc-v1-1-380f29ba4a16@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-29Add support for GPIO based CSMark Brown
Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>: The Microchip PolarFire SoC SPI "hard" controller supports eight chip selects. However, only one chip select is physically wired. Therefore, use GPIO descriptors to configure additional chip select lines.
2024-05-29Add optional reset control for Cadence SPIMark Brown
Merge series from Ji Sheng Teoh <jisheng.teoh@starfivetech.com>: The first patch adds optional reset control to support assertion and deassertion of reset signal to properly bring the SPI device into an operating condition. The second patch documents the optional reset control into dt-bindings.
2024-05-27spi: dt-bindings: Document the IBM FSI-attached SPI controllerEddie James
IBM Power processors have a SPI controller that can be accessed over FSI from a service processor. Document it. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20240514192630.152747-1-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27spi: dt-bindings: brcm,bcm2835-spi: convert to dtschemaKanak Shilledar
Convert the Broadcom BCM2835 SPI0 controller to newer DT schema. Created DT schema based on the .txt file which had `comaptible`, `reg`, `interrupts`, `clocks` as required properties. Added GPL-2.0 OR BSD-2-Clause License Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240514070051.2959-1-kanakshilledar111@protonmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27spi: dt-bindings: marvell,mmp2-ssp: Merge PXA SSP into schemaRob Herring (Arm)
The Marvell PXA SSP block is the same or similiar to the MMP2 variant. The only difference in the binding is the PXA version supports DMA (and that's probably a binding difference rather than an actual h/w difference). The old binding didn't belong under 'serial' as it is not a UART. The SSP block also supports audio devices, so 'spi' is not a perfect fit either. As the existing schema for MMP2 is there, just leave things as-is. The examples in the old text binding were pretty out of sync with reality. 'clock-names' and 'ssp-id' aren't documented nor used. Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://msgid.link/r/20240522132859.3146335-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27spi: dt-bindings: Add num-cs property for mpfs-spiPrajna Rajendra Kumar
The PolarFire SoC SPI "hard" controller supports eight CS lines, out of which only one CS line is physically wired. The default value of 'num-cs' was never set and it did not didn't impose a maximum value. To reflect this hardware limitation in the device tree, the binding enforces that the 'num-cs' property cannot exceed 1 unless additional CS lines are explicitly defined using GPIO descriptors. Fixes: 2da187304e55 ("spi: add bindings for microchip mpfs spi") Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Link: https://msgid.link/r/20240514104508.938448-2-prajna.rajendrakumar@microchip.com Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27spi: dt-bindings: spi-cadence: Add optional reset controlJi Sheng Teoh
Document the optional reset control to SPI. Co-developed-by: Eng Lee Teh <englee.teh@starfivetech.com> Signed-off-by: Eng Lee Teh <englee.teh@starfivetech.com> Co-developed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20240508054728.1751162-3-jisheng.teoh@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-14Merge tag 'spi-v6.10' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The diffstat for this release is dominated by the new Airoha driver, mainly as a result of this being a generally quite quiet release. There were a couple of cleanups in the core but nothing substantial, the updates here are almost all driver specific ones. - Support for multi-word mode in the OMAP2 McSPI driver - Overhaul of the PXA2xx driver, mostly API updates - A number of DT binding conversions - Support for Airoha NAND controllers, Cirrus Logic CS35L56, Mobileye EYEQ5 and Renesas R8A779H0" * tag 'spi-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits) spi: dw: Bail out early on unsupported target mode spi: Remove unneded check for orig_nents MAINTAINERS: repair file entry in AIROHA SPI SNFI DRIVER spi: pxa2xx: Drop the stale entry in documentation TOC spi: pxa2xx: Don't provide struct chip_data for others spi: pxa2xx: Remove timeout field from struct chip_data spi: pxa2xx: Remove DMA parameters from struct chip_data spi: pxa2xx: Drop struct pxa2xx_spi_chip spi: pxa2xx: Don't use "proxy" headers spi: pxa2xx: Remove outdated documentation spi: pxa2xx: Move contents of linux/spi/pxa2xx_spi.h to a local one spi: pxa2xx: Provide num-cs for Sharp PDAs via device properties spi: pxa2xx: Allow number of chip select pins to be read from property spi: dt-bindings: ti,qspi: convert to dtschema spi: bitbang: Add missing MODULE_DESCRIPTION() spi: bitbang: Use NSEC_PER_*SEC rather than hard coding spi: dw: Drop default number of CS setting spi: dw: Convert dw_spi::num_cs to u32 spi: dw: Add a number of native CS auto-detection spi: dw: Convert to using BITS_TO_BYTES() macro ...
2024-05-03spi: dt-bindings: ti,qspi: convert to dtschemaKousik Sanagavarapu
Convert txt binding of TI's qspi controller (found on their omap SoCs) to dtschema to allow for validation. The changes, w.r.t. the original txt binding, are: - Introduce "clocks" and "clock-names" which was never mentioned. - Reflect that "ti,hwmods" is deprecated and is not a "required" property anymore. - Introduce "num-cs" which allows for setting the number of chip selects. - Drop "qspi_ctrlmod". Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501165203.13763-1-five231003@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-30spi: dt-bindings: airoha: Add YAML schema for SNFI controllerLorenzo Bianconi
Introduce Airoha EN7581 SPI NAND controller binding Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/f3377b323f00589e6b7ed7950c4840d18129238b.1714377864.git.lorenzo@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-21spi: dt-bindings: armada-3700: convert to dtschemaKousik Sanagavarapu
Convert txt binding of marvell armada 3700 SoC spi controller to dtschema to allow for validation. Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240417052729.6612-1-five231003@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-17spi: renesas,sh-msiof: Add r8a779h0 supportGeert Uytterhoeven
Document support for the Clock-Synchronized Serial Interface with FIFO (MSIOF) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/68a4d8ad8638c1133e21d0eef87e8982ddea3dd8.1713279687.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-10spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optionalThéo Lebrun
Make cdns,fifo-depth devicetree property optional. Value can be detected at runtime. Upper SRAMPARTITION register bits are read-only. Procedure to find FIFO depth is therefore to write 0xFFFFFFFF and read back to get amount of writeable bits. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240410-cdns-qspi-mbly-v3-3-7b7053449cf7@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-10spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatibleThéo Lebrun
Add Mobileye EyeQ5 compatible. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240410-cdns-qspi-mbly-v3-2-7b7053449cf7@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-10spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabeticallyThéo Lebrun
Compatibles are ordered by date of addition. Switch to (deterministic) alphabetical ordering. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240410-cdns-qspi-mbly-v3-1-7b7053449cf7@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-05dt-bindings: treewide: add access-controllers descriptionGatien Chevallier
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controller. It allows an accurate representation of the hardware, where various peripherals are connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-03-05spi: dt-bindings: introduce FIFO depth propertiesTudor Ambarus
There are SPI IPs that can be configured by the integrator with a specific FIFO depth depending on the system's capabilities. For example, the samsung USI SPI IP can be configured by the integrator with a TX/RX FIFO from 8 byte to 256 bytes. Introduce the ``fifo-depth`` property for such instances of IPs where the same FIFO depth is used for both RX and TX. Introduce ``rx-fifo-depth`` and ``tx-fifo-depth`` properties for cases where the RX FIFO depth is different from the TX FIFO depth. Make the dedicated RX/TX properties dependent on each other and mutual exclusive with the other. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240216070555.2483977-2-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-03-04spi: dt-bindings: samsung: make dma properties not requiredTudor Ambarus
Since the addition of the driver in 2009, the driver selects between DMA and polling mode depending on the transfer length - DMA mode for transfers bigger than the FIFO depth, polling mode otherwise. All versions of the IP support polling mode, make the dma properties not required. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://msgid.link/r/20240301115546.2266676-1-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-28spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from listVarshini Rajendran
Remove microchip,sam9x60-spi compatible from the list as the driver used has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the same compatible as fallback. So removing the microchip,sam9x60-spi compatible from the list since it is not needed. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://msgid.link/r/20240223172638.672366-1-varshini.rajendran@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-08spi: dt-bindings: samsung: add google,gs101-spi compatibleTudor Ambarus
Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240207111516.2563218-2-tudor.ambarus@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-24spi: dt-bindings: samsung: Add Exynos850 SPISam Protsenko
Document samsung,exynos850-spi compatible which will be used on Exynos850 SoC. Exynos850 doesn't have ioclk, so only two clocks are needed (bus clock and functional SPI clock). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20240120012948.8836-3-semen.protsenko@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-22dt-bindings: spi: nxp-fspi: support i.MX93 and i.MX95Peng Fan
Add i.MX93/95 flexspi compatible strings, which are compatible with i.MX8MM Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240122091510.2077498-2-peng.fan@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-01-22dt-bindings: spi: fsl-lpspi: support i.MX95 LPSPIPeng Fan
Add i.MX95 LPSPI compatible string, same as i.MX93 compatible with i.MX7ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20240122091510.2077498-1-peng.fan@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-12-21dt-bindings: spi: stm32: add st,stm32mp25-spi compatibleValentin Caron
Add st,stm32mp25-spi compatible in dt-bindings. STM32MP25 spi is similar to the STM32H7 except for the following two points: - Burst should not be enabled with the new DMA used on STM32MP25. - STM32MP25 SPI8 has a limited feature set, it can only send words of 8 or 16 bits and with a maximum words number of 1024. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://msgid.link/r/20231218155721.359198-3-alain.volmat@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-03-24 17:56:54 +0000