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2025-04-24dt-bindings: soc: renesas: Document Retronix R-Car V4H Sparrow Hawk board ↵Marek Vasut
support Document Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250420173829.200553-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-24dt-bindings: vendor-prefixes: Add Retronix Technology Inc.Marek Vasut
Add vendor prefix for Retronix Technology Inc. https://www.retronix.com.tw/en/about.html Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/20250420173829.200553-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-24dt-bindings: arm: mediatek: Add MT8186 Ponyta ChromebookJianeng Ceng
Ponyta is a custom label Chromebook based on MT8186. It is a self-developed project of Huaqin and has no fixed OEM. Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250424010850.994288-2-cengjianeng@huaqin.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-04-23dt-bindings: interrupt-controller: via,vt8500-intc: Convert to YAMLAlexey Charkov
Rewrite the textual description for the VIA/WonderMedia interrupt controller as YAML schema. The original textual version did not contain information about the usage of 'interrupts' to describe the connection of a chained controller to its parent, add it here. A chained controller can trigger up to 8 different interrupts (IRQ0~7) on its parent. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250418-via_intc_binding-v2-1-b649ce737f71@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-04-23dt-bindings: arm/cpus: allow up to 3 interconnects entriesNeil Armstrong
Allow up to 3 entries as used on the Qualcomm SM8650 CPU nodes. This fixes the following errors: cpu@0: interconnects: [[7, 3, 3, 7, 15, 3], [8, 0, 3, 8, 1, 3], [9, 0, 9, 1]] is too long Fixes: 791a3fcd2345 ("dt-bindings: arm/cpus: Add missing properties") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250418-topic-sm8x50-upstream-cpu-icc-max3-v1-1-87d9c2713d72@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-04-23dt-bindings: display: Add Sitronix ST7571 LCD ControllerMarcus Folkesson
Sitronix ST7571 is a dot matrix LCD controller supporting both 4bit grayscale and monochrome LCDs. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Link: https://lore.kernel.org/r/20250423-st7571-v6-1-e9519e3c4ec4@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-04-23dt-bindings: hwmon: ti,tmp102: document optional V+ supply propertyPeter Korsgaard
TMP102 is powered by its V+ supply, document it. The property is called "vcc-supply" since the plus sign (+) is not a valid property character. Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250417180426.3872314-1-peter@korsgaard.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-04-23dt-bindings: hwmon: pmbus: add lt3074Cedric Encarnacion
Add Analog Devices LT3074 Ultralow Noise, High PSRR Dropout Linear Regulator. Signed-off-by: Cedric Encarnacion <cedricjustine.encarnacion@analog.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250421-upstream-lt3074-v3-1-71636322f9fe@analog.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-04-23dt-bindings: hwmon: amc6821: add fan and PWM outputFrancesco Dolcini
Add properties to describe the fan and the PWM controller output. Link: https://www.ti.com/lit/gpn/amc6821 Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250402102146.65406-2-francesco@dolcini.it Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-04-23dt-bindings: wireless: qcom,wcnss: Use wireless-controller.yamlDavid Heidelberg
Reference wireless-controller.yaml schema, so we can use properties as local-mac-address or mac-address. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://patch.msgid.link/20250324-dt-bindings-network-class-v5-5-f5c3fe00e8f0@ixit.cz Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-04-23dt-bindings: wireless: silabs,wfx: Use wireless-controller.yamlJanne Grunau
Instead listing local-mac-address and mac-address properties, reference wireless-controller.yaml schema. The schema brings in constraints for the property checked during `make dtbs_check`. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Jérôme Pouiller <jerome.pouiller@silabs.com> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://patch.msgid.link/20250324-dt-bindings-network-class-v5-4-f5c3fe00e8f0@ixit.cz Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-04-23dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schemaJanne Grunau
The wireless-controller schema specifies local-mac-address as used in the bcm4329-fmac device nodes of Apple silicon devices (arch/arm64/boot/dts/apple). Fixes `make dtbs_check` for those devices. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://patch.msgid.link/20250324-dt-bindings-network-class-v5-3-f5c3fe00e8f0@ixit.cz Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-04-23dt-bindings: net: Add generic wireless controllerDavid Heidelberg
Wireless controllers share the common properties. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://patch.msgid.link/20250324-dt-bindings-network-class-v5-2-f5c3fe00e8f0@ixit.cz Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-04-23dt-bindings: net: Add network-class schema for mac-address propertiesJanne Grunau
The ethernet-controller schema specifies "mac-address" and "local-mac-address" but other network devices such as wireless network adapters use mac addresses as well. The Devicetree Specification, Release v0.3 specifies in section 4.3.1 a generic "Network Class Binding" with "address-bits", "mac-address", "local-mac-address" and "max-frame-size". This schema specifies the "address-bits" property and moves the remaining properties over from the ethernet-controller.yaml schema. The "max-frame-size" property is used to describe the maximal payload size despite its name. Keep the description from ethernet-controller specifying this property as MTU. The contradictory description in the Devicetree Specification is ignored. Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250324-dt-bindings-network-class-v5-1-f5c3fe00e8f0@ixit.cz Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-04-23dt-bindings: dma: fsl-edma: increase maxItems of interrupts and interrupt-namesJoy Zou
The edma controller support optional error interrupt, so update interrupts and interrupt-names's maxItems. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250407-edma_err-v2-1-9d7e5b77fcc4@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-23dt-bindings: dma: qcom,bam: Document dma-coherent propertyKaushal Kumar
Qualcomm BAM DMA controller has DMA-coherent support so define it in the properties section. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Link: https://lore.kernel.org/r/20250423063054.28795-3-quic_kaushalk@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-23dt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirementKonrad Dybcio
Certain platforms (such as Chrome SDM845 and SC7180 with a TF-A running as secure firmware) do not have a OSI-mode capable PSCI implementation. That in turn means the PSCI-associated power domain which represents the system's power state can't provide enough feedback to the RSC device. Don't require power-domains on platforms where this may be the case. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-1-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-23dt-bindings: power: rockchip: Add support for RK3562 SoCFinley Xiao
According to a description from TRM, add all the power domains. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250415032314.44997-1-kever.yang@rock-chips.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-04-23Add RK3576 SAI Audio Controller SupportMark Brown
Merge series from Nicolas Frattaroli <nicolas.frattaroli@collabora.com>: This series adds support for Rockchip's Serial Audio Interface (SAI) controller, found on SoCs such as the RK3576. The SAI is a flexible controller IP that allows both transmitting and receiving digital audio in the I2S, TDM and PCM formats. Instances of this controller are used both for externally exposed audio interfaces, as well as for audio on video interfaces such as HDMI.
2025-04-23dt-bindings: pinctrl: convert fsl,imx7ulp-pinctrl.txt to yaml formatFrank Li
Convert fsl,imx7ulp-pinctrl.txt to yaml format. Additional changes: - remove label in example - fsl,pin direct use hex value instead of macro because macro define in dts local directory. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250417152158.3570936-1-Frank.Li@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-23media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G3E SoCTommaso Merciai
The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five interrupts: - image_conv: image_conv irq - axi_mst_err: AXI master error level irq - vd_addr_wend: Video data AXI master addr 0 write end irq - sd_addr_wend: Statistics data AXI master addr 0 write end irq - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq This IP has only one input port 'port@1' similar to the RZ/G2UL CRU. Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G3E CSI-2 blockTommaso Merciai
Document the CSI-2 block which is part of CRU found in Renesas RZ/G3E SoC. The CSI-2 block on the RZ/G3E SoC is identical to one found on the RZ/V2H(P) SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-3-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoCLad Prabhakar
The MIPI CSI-2 block on the Renesas RZ/V2H(P) SoC is similar to the one found on the Renesas RZ/G2L SoC, with the following differences: - A different D-PHY - Additional registers for the MIPI CSI-2 link - Only two clocks Add a new compatible string, `renesas,r9a09g057-csi2`, for the RZ/V2H(P) SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoCLad Prabhakar
The FCPVD block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,fcpv` will be used as a fallback compatible string on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20250408193158.80936-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P)Lad Prabhakar
The VSPD block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,r9a07g044-vsp2` will be used as a fallback compatible string on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20250408193158.80936-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23dt-bindings: pinctrl: spacemit: add clock and reset propertyYixun Lan
SpacemiT K1 SoC's pinctrl controller requires two clocks in order to work properly, also has one reset line from hardware perspective. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250416-02-k1-pinctrl-clk-v2-1-2b5fcbd4183c@gentoo.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-23dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOSAngeloGioacchino Del Regno
Add support for the Power Domains (MTCMOS) integrated into the MediaTek Dimensity 1200 (MT6893) SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250410143944.475773-2-angelogioacchino.delregno@collabora.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-04-23dt-bindings: PCI: qcom: Add IPQ5018 SoCNitheesh Sekar
Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250326-ipq5018-pcie-v7-3-e1828fef06c9@outlook.com
2025-04-23dt-bindings: PCI: Remove obsolete .txt docsRob Herring (Arm)
The content in these files has been moved to the schemas in dtschema. pci.txt is covered by pci-bus-common.yaml and pci-host-bridge.yaml. pci-iommu.txt is covered by pci-iommu.yaml. pci-msi.txt is covered in msi-map property in pci-host-bridge.yaml. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: Frank Li <Frank.li@nxp.com> Link: https://patch.msgid.link/20250404221559.552201-1-robh@kernel.org
2025-04-23dt-bindings: PCI: Convert marvell,armada8k-pcie to schemaRob Herring (Arm)
Convert the marvell,armada8k-pcie binding to DT schema. The binding uses different names for reg, clocks, and phys which have to be added to the common Synopsys DWC binding. The "marvell,reset-gpio" property was not documented. Mark it deprecated as the "reset-gpios" property can be used instead. The "msi-parent" property was also not documented. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250414214135.1680076-1-robh@kernel.org
2025-04-23dt-bindings: PCI: Convert Marvell EBU to schemaRob Herring (Arm)
Convert the Marvell EBU (Kirkwood, Dove, Armada XP/370) to DT schema format. Add "error" to interrupt-names which is in use, but missing. Shorten the example from 10 child nodes to 6 as the additional ones don't add much value to the example. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250414214157.1680484-1-robh@kernel.org
2025-04-23dt-bindings: PCI: sifive,fu740-pcie: Fix include placement in DTS exampleKrzysztof Kozlowski
Coding style and common logic dictates that headers should not be included in device nodes. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250324125202.81986-2-krzysztof.kozlowski@linaro.org
2025-04-23dt-bindings: PCI: Correct indentation and style in DTS exampleKrzysztof Kozlowski
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250324125202.81986-1-krzysztof.kozlowski@linaro.org
2025-04-23dt-bindings: PCI: dwc: rockchip: Add rk3562 supportKever Yang
rk3562 is using the same dwc controller as rk3576. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250415051855.59740-2-kever.yang@rock-chips.com
2025-04-23dt-bindings: PCI: dw: rockchip: Add rk3576 supportKever Yang
rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC instead of using GIC ITS, so - no ITS support is required and the 'msi-map' is not required, - a new 'msi' interrupt is needed. Co-developed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [mani: changed 'its' to 'ITS' in the binding, spelling mistake fix] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20250414145110.11275-2-kever.yang@rock-chips.com
2025-04-22dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETHLad Prabhakar
GBETH IP on the Renesas RZ/V2H(P) SoC is integrated with Synopsys DesignWare MAC (version 5.20). Document the device tree bindings for the GBETH glue layer. Generic compatible string 'renesas,rzv2h-gbeth' is added since this module is identical on both the RZ/V2H(P) and RZ/G3E SoCs. The Rx/Tx clocks supplied for GBETH on the RZ/V2H(P) SoC is depicted below: Rx / Tx -------+------------- on / off ------- | | Rx-180 / Tx-180 +---- not ---- on / off ------- Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250417084015.74154-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-04-22dt-bindings: net: dwmac: Increase 'maxItems' for 'interrupts' and ↵Lad Prabhakar
'interrupt-names' Increase the `maxItems` value for the `interrupts` and `interrupt-names` properties to 11 to support additional per-channel Tx/Rx completion interrupts on the Renesas RZ/V2H(P) SoC, which features the `snps,dwmac-5.20` IP. Refactor the `interrupt-names` property by replacing repeated `enum` entries with a `oneOf` list. Add support for per-channel receive and transmit completion interrupts using regex patterns. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250417084015.74154-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-04-22dt-bindings: net: dp83822: add constraints for mac-termination-ohmsDimitri Fedrau
Property mac-termination-ohms is defined in ethernet-phy.yaml. Add allowed values for the property. Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250416-dp83822-mac-impedance-v3-2-028ac426cddb@liebherr.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-04-22dt-bindings: net: ethernet-phy: add property mac-termination-ohmsDimitri Fedrau
Add property mac-termination-ohms in the device tree bindings for selecting the resistance value of the builtin series termination resistors of the PHY. Changing the resistance to an appropriate value can reduce signal reflections and therefore improve signal quality. Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250416-dp83822-mac-impedance-v3-1-028ac426cddb@liebherr.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-04-22dt-bindings: iio: imu: icm42600: add interrupt naming supportJean-Baptiste Maneyrol
Add interrupt-names field for specifying interrupt pin configured. Chips are supporting up to 2 interrupt pins with configurable interrupt sources. Change interrupt to support 1 or 2 entries. Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250410-iio-imu-inv-icm42600-rework-interrupt-using-names-v4-1-19e4e2f8f7eb@tdk.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: ROHM BD79104 ADCMatti Vaittinen
The ROHM BD79104 is a 12-bit, 8-channel ADC with two power supply pins, connected to SPI. It's worth noting the IC requires SPI MODE 3, (CPHA = 1, CPOL = 1). I used an evaluation board "BD79104FV-EVK-001" from ROHM. With this board I had problems to have things working correctly with higher SPI clock frequencies. I didn't do thorough testing for maximum frequency though. First attempt was 40M, then 20M and finally 4M. With 20M it seemed as if the read values were shifted by 1 bit. With 4M it worked fine. The component data-sheet is not exact what comes to the maximum SPI frequency. It says SPI frequency is 20M - "unless othervice specified". Additionally, it says that maximum sampling rate is 1Mhz, and since reading a sample requires writing the channel (16 bits) and reading data (16 bits) - we get some upper limit from this. >From the "frequency is 20M, unless othervice specified" I picked the maximum frequency 20M - and did assumption that my problems with 20M weren't related to the BD79104 - but to the evaluation board "BD79104FV-EVK-001". Add bindings for the ROHM BD79104 ADC. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/2a4c65ee35cb79c6b29dbc59cfd9bc7d615a08ac.1744022065.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: adc: adi,ad7606: add SPI offload propertiesAngelo Dureghello
Add #trigger-source-cells property to allow the BUSY output to be used as a SPI offload trigger source to indicate when a sample is ready to be read. Macros are added to adi,ad7606.h for the cell values to help with readability since they are arbitrary values. Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250403-wip-bl-spi-offload-ad7606-v1-1-1b00cb638b12@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: adc: ad7380: add AD7389-4David Lechner
Add compatible and quirks for AD7389-4. This is essentially the same as AD7380-4 but instead of having no internal reference, it has no external reference voltage supply. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250401-iio-ad7380-add-ad7389-4-v1-1-23d2568aa24f@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: Add ROHM BD7970x variantsMatti Vaittinen
The ROHM BD79700, BD79701 and BD79702 are subsets of the BD79703 DAC. The main difference is the number of the channels. BD79703 has 6 channels. The BD79702 has 4, BD79701 3 and BD79700 2 channels. Additionally, the BD79700 and BD79701 do not have separate Vfs pin but use the Vcc also for the full-scale voltage. Add properties for the BD79700, BD79701 and BD79702. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/0a114565e4de52bf8f98c4f9d17943e5148b0112.1743576022.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: ROHM BD79124 ADC/GPOMatti Vaittinen
Add binding document for the ROHM BD79124 ADC / GPO. ROHM BD79124 is a 8-channel, 12-bit ADC. The input pins can also be used as general purpose outputs. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/e16f54b6214b0d796216729a7e29b8f7be9ae19e.1742560649.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: filter: Add lpf/hpf freq marginsSam Winchenbach
Adds two properties to add a margin when automatically finding the corner frequencies. Signed-off-by: Sam Winchenbach <swinchenbach@arka.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250328174831.227202-2-sam.winchenbach@framepointer.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: adc: amlogic,meson-saradc: Add GXLX SoC compatibleMartin Blumenstingl
Add a compatible string for the GXLX SoC. It's very similar to GXL but has three additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks. Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20250330101922.1942169-2-martin.blumenstingl@googlemail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: light: bh1750: Add reset-gpios propertySergio Perez
Some BH1750 sensors require a hardware reset via GPIO before they can be properly detected on the I2C bus. Add a new reset-gpios property to the binding to support this functionality. The reset-gpios property allows specifying a GPIO that will be toggled during driver initialization to reset the sensor. Signed-off-by: Sergio Perez <sergio@pereznus.es> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250324135920.6802-1-sergio@pereznus.es Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: Use unevaluatedProperties for SPI devicesKrzysztof Kozlowski
SPI devices should use unevaluatedProperties:false instead of additionalProperties:false, to allow any SPI device properties listed in spi-peripheral-props.yaml. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com> Link: https://patch.msgid.link/20250324125313.82226-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-04-22dt-bindings: iio: Correct indentation and style in DTS exampleKrzysztof Kozlowski
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250324125313.82226-1-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
generated by cgit (git 2.34.1) at 2025-09-24 00:45:34 +0000