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2025-06-18dt-bindings: clock: Convert cirrus,ep7209-clk to DT schemaRob Herring (Arm)
Convert the Cirrus EP7xxx (aka CLPS711x) binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004923.1795927-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-06-18dt-bindings: clock: Convert APM XGene clocks to DT schemaRob Herring (Arm)
Convert the APM XGene clocks to DT schema. The device clock binding is a bit different from the others, so put it in its own schema file. Drop the examples. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004655.1792703-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-06-18dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schemaRob Herring (Arm)
Convert the Axis ARTPEC-6 clock controller to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004647.1792464-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-06-18dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schemaRob Herring (Arm)
Convert the Broadcom BCM53573 ILP clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004618.1791669-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-06-18Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' ↵Bjorn Andersson
into clk-for-6.17 Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the newly introduced clock constants to be made available to the DeviceTree branch as well.
2025-06-18dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoCLuo Jie
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference input clock. The output clocks are the same as IPQ9574 SoC, except for the clock rate of output clocks to PPE and NSS. Also, add the new header file to export the CMN PLL output clock specifiers for IPQ5424 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-18dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 PlusAndré Apitzsch
BQ Aquaris X5 Plus (Longcheer L9360) is a smartphone based on MSM8976 SoC. Signed-off-by: André Apitzsch <git@apitzsch.eu> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250615-bqx5plus-v2-2-72b45c84237d@apitzsch.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-18ASoC: dt-bindings: cirrus,cs42xx8: add 'port' propertyLaurentiu Mihalcea
The cs42xx8 codecs may be used with audio graph card and thus may require an additional property: 'port'. Add it. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20250617144619.1130857-1-laurentiumihalcea111@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-06-18dt-bindings: rockchip: pmu: Add compatible for RK3528Jonas Karlman
Add the compatible for the pmu mfd on RK3528 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250518220707.669515-4-jonas@kwiboo.se Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-06-18dt-bindings: power: rockchip: Add support for RK3528Jonas Karlman
Add the compatible string and power domains for RK3528 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-06-18dt-bindings: pinctrl: eswin: Document for EIC7700 SoCYulin Lu
Add EIC7700 pinctrl device for all configurable pins. For the EIC7700 pinctrl registers, each register (32 bits) controls the characteristics of a single pin. It supports setting function multiplexing, Schmitt trigger, drive strength, pull-up/pull-down, and input enable. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250612104811.1206-1-luyulin@eswincomputing.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-18dt-bindings: gpio: arm,pl061: Drop interrupt properties as requiredRob Herring (Arm)
It is possible that the PL061 doesn't have any interrupt connected and can't be an interrupt provider, so drop the interrupt properties as required. The LG LG131x SoCs are one example of this. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250609220900.3035642-1-robh@kernel.org [Bartosz: g/pl011/pl061/] Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-06-18dt-bindings: pinctrl: stm32: Add RSVD mux functionFabien Dessenne
Document the RSVD (Reserved) mux function, used to reserve pins for a coprocessor not running Linux. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250610152309.299438-3-antonio.borneo@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-18dt-bindings: mtd: convert nxp-spifi.txt to yaml formatFrank Li
Convert nxp-spifi.txt to yaml format. Additional changes: - ref /schemas/spi/spi-controller.yaml. - remove label in example. - change node name to spi in example. - remove child node in example. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-06-18media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible stringsRobert Chiras
Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove fsl,mipi-phy-gpr from required properties and add new reg space, since i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space. Keep the same restriction for other compatible strings. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-8-d4be869fdb7e@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-06-18media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISIFrank Li
Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names, power-domains, and ports differ significantly from the existing nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches. Add new file to MAINTAINERS. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-1-d4be869fdb7e@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-06-17dt-bindings: sram: qcom,imem: Add a number of missing compatiblesKonrad Dybcio
Currently described or not, IMEM is present on *all* Qualcomm SoCs. Preemptively add a number of compatibles to ease integration. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250523-topic-ipa_mem_dts-v1-1-f7aa94fac1ab@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-18Merge tag 'drm-misc-next-2025-06-12' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.17: UAPI Changes: Cross-subsystem Changes: Core Changes: - atomic-helpers: Tune the enable / disable sequence - bridge: Add destroy hook - color management: Add helpers for hardware gamma LUT handling - HDMI: Add CEC handling, YUV420 output support - sched: tracing improvements Driver Changes: - hyperv: Move out of simple-kms, drm_panic support - i915: drm_panel_follower support - imx: Add IMX8qxq Display Controller Support - lima: Add Rockchip RK3528 GPU Support - nouveau: fence handling cleanup - panfrost: Add BO labeling, 64-bit registers access - qaic: Add RAS Support - rz-du: Add RZ/V2H(P) Support, MIPI-DSI DCS Support - sun4i: Add H616 Support - tidss: Add TI AM62L Support - vkms: YUV and R* formats support - bridges: - Switched to reference counted drm_bridge allocations - panels: - Switched to reference counted drm_panel allocations - Add support for fwnode-based panel lookup - himax-hx8394: Support for Huiling hl055fhv028c - ilitek-ili9881c: Support for 7" Raspberry Pi 720x1280 - panel-edp: Support for KDC KD116N3730A05, N160JCE-ELL CMN, - panel-simple: Support for AUO P238HAN01 - st7701: Support for Winstar wf40eswaa6mnn0 - visionox-rm69299: Support for rm69299-shift - New panels: Renesas R61307, Renesas R69328 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://lore.kernel.org/r/20250612-coucal-of-impossible-cleaning-a5eecf@houat
2025-06-17Merge tag 'libnvdimm-fixes-6.16-rc3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm Pull libnvdimm fix from Ira Weiny: "This converts the pmem-region device tree bindings to YAML to fix errors and bring it up to date" * tag 'libnvdimm-fixes-6.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm: dt-bindings: pmem: Convert binding to YAML
2025-06-17dt-bindings: arm: cpus: Add Kryo 470 CPUsDanila Tikhonov
Document Kryo 470 CPUs found in Qualcomm Snapdragon 730/730G/732G (SM7150). Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-1-bf9a9081631d@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: sram: qcom,imem: Add the SM7150 compatibleDanila Tikhonov
Add compatible for SM7150 SoC IMEM. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-5-bf9a9081631d@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: soc: qcom: aoss-qmp: Add the SM7150 compatibleDavid Wronek
Document the AOSS QMP compatible for SM7150. Signed-off-by: David Wronek <david@mainlining.org> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-6-bf9a9081631d@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: soc: qcom,dcc: Add the SM7150 compatibleDanila Tikhonov
Document DDC compatible for SM7150. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-12-bf9a9081631d@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: soc: qcom: add qcom,qcs615-imem compatibleLijuan Gao
Document qcom,qcs615-imem compatible. It has a child node for debugging purposes. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20250526-add_qcs615_remoteproc_support-v4-2-06a7d8bed0b5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: HID: i2c-hid: elan: Introduce Elan eKTH8D18Chen-Yu Tsai
The Elan eKTH8D18 touchscreen controller is an I2C HID device with a longer boot-up time. Power sequence timing wise it is compatible with the eKTH6A12NAY, with a power-on delay of at least 5ms, 20ms out-of-reset for I2C ack response, and 150ms out-of-reset for I2C HID enumeration, both shorter than what the eKTH6A12NAY requires. Enumeration and subsequent operation follows the I2C HID standard. Add a compatible string for it with the ekth6a12nay one as a fallback. No enum was used as it is rare to actually add new entries. These chips are commonly completely backward compatible, and unless the power sequencing delays change, there is no real effort being made to keep track of new parts, which come out constantly. Also drop the constraints on the I2C address since it's not really part of the binding. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20250617082004.1653492-2-wenst@chromium.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-06-17dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6Hans Zhang
Update the PCI Endpoint (EP) device tree binding documentation to include PCIe Gen5 and Gen6 support for the `max-link-speed` property. Similar to the Host Controller binding, the original EP binding limited this value to 1~4 (Gen1~Gen4). With current SoCs requiring Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns the EP binding with the kernel's PCIe 6.0 capabilities. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250529021026.475861-3-18255117159@163.com
2025-06-17dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300Ziyue Zhang
QCS8300 is derived from SA8775p. Hence, add the callback with SA8775p as the fallback. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250529035635.4162149-3-quic_ziyuzhan@quicinc.com
2025-06-17dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615Ziyue Zhang
QCS615 is derived from SM8150. Hence, add the callback with SM8150 as the fallback. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> [mani: commit message rewording] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250527072036.3599076-3-quic_ziyuzhan@quicinc.com
2025-06-17dt-bindings: remoteproc: qcom,sa8775p-pas: Correct the interrupt numberLijuan Gao
Correct the interrupt number of ready and handover in the DTS example. Fixes: af5da7b0944c ("dt-bindings: remoteproc: qcom,sa8775p-pas: Document the SA8775p ADSP, CDSP and GPDSP") Signed-off-by: Lijuan Gao <lijuan.gao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250612-correct_interrupt_for_remoteproc-v1-1-490ee6d92a1b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-17dt-bindings: gpio: gpio-xilinx: Mark clocks as required propertyMichal Simek
On Microblaze platforms there is no need to handle clocks because the system is starting with clocks enabled (can be described via fixed clock node or clock-frequency property or not described at all). With using soft IPs with SOC platforms there is mandatory to handle clocks as is explained in commit 60dbdc6e08d6 ("dt-bindings: net: emaclite: Add clock support"). That's why make clock as required in dt binding because it is present in both configurations and should be described even there is no way how to handle it on Microblaze systems. There is also need to describe missing axi gpio clock in fpga-region.yaml not to introduce new error when make dt_binding_check runs. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> # fpga Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/94151cfbcff5e4ae05894981c7e398b605d4b00a.1750059796.git.michal.simek@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-06-17dt-bindings: dmaengine: Add dma multiplexer for CV18XX/SG200X series SoCInochi Amaoto
The DMA IP of Sophgo CV18XX/SG200X is based on a DW AXI CORE, with an additional channel remap register located in the top system control area. The DMA channel is exclusive to each core. In addition, the DMA multiplexer is a subdevice of system controller, so this binding only contains necessary properties for the multiplexer itself. Add the dmamux binding for CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250611081000.1187374-2-inochiama@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-16dt-bindings: clock: Add RaspberryPi RP1 clock bindingsAndrea della Porta
Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in MAINTAINERS file. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-16media: dt-bindings: media: renesas,vsp1: Document RZ/V2N SoCLad Prabhakar
The VSPD block on the RZ/V2N SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,r9a07g044-vsp2` will be used as a fallback compatible string on the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250530154148.374663-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-06-16media: dt-bindings: media: renesas,fcp: Document RZ/V2N SoCLad Prabhakar
The FCPVD block on the RZ/V2N SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,fcpv` will be used as a fallback compatible string on the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250530154148.374663-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-06-15dt-bindings: phy: Add the M31 based eUSB2 PHY bindingsWesley Cheng
On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the binding definition for the PHY driver. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-2-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHYWesley Cheng
Add an entry to the compatible field for SM8750 for the QMP combo PHY. This handles the USB3 path for SM8750. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-1-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: renesas,usb2-phy: Document RZ/V2N SoC supportLad Prabhakar
Document support for the USB2.0 phy found on the Renesas RZ/V2N (R9A09G056) SoC. The USB2.0 phy is functionally identical to that on the RZ/V2H(P) SoC, so no driver changes are needed. The existing `renesas,usb2-phy-r9a09g057` compatible will be used as a fallback for the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250528133858.168582-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert Marvell MVEBU PHYs to DT schemaRob Herring (Arm)
Convert the Marvell Armada-375 USB and MVEBU SATA PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250607212609.743346-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert marvell,armada-380-comphy to DT schemaRob Herring (Arm)
Convert the Marvell Armada 38x combo PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250607212541.742427-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert ti,keystone-usbphy to DT schemaRob Herring (Arm)
Convert the TI Keystone USB PHY binding to DT schema format. Drop the "#address-cells" and "#size-cells" properties which don't make sense without any child nodes. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212641.744683-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert ti,dm816x-usb-phy to DT schemaRob Herring (Arm)
Convert the TI DM816x USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212634.744373-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert st,spear1310-miphy to DT schemaRob Herring (Arm)
Convert the ST SPEAr MIPHY PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212629.744191-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert qca,ar7100-usb-phy to DT schemaRob Herring (Arm)
Convert the Qualcomm-Atheros AR7100 USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212625.744008-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert motorola,mapphone-mdm6600 to DT schemaRob Herring (Arm)
Convert the Motorola Mapphone MDM6600 USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212621.743859-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert motorola,cpcap-usb-phy to DT schemaRob Herring (Arm)
Convert the Motorola CPCAP PMIC USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212616.743674-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert marvell,mmp2-usb-phy to DT schemaRob Herring (Arm)
Convert the Marvell MMP2 USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212613.743515-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert marvell,comphy-cp110 to DT schemaRob Herring (Arm)
Convert the Marvell CP110 combo PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212605.743176-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert marvell,berlin2-usb-phy to DT schemaRob Herring (Arm)
Convert the Marvell Berlin2 USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212554.742884-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert marvell,berlin2-sata-phy to DT schemaRob Herring (Arm)
Convert the Marvell Berlin2 SATA PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212545.742617-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15dt-bindings: phy: Convert lantiq,ase-usb2-phy to DT schemaRob Herring (Arm)
Convert the Lantiq XWAY USB PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212537.742287-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-20 12:35:38 +0000