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2025-05-14dt-bindings: arm: qcom: Document HP EliteBook Ultra G1qJuerg Haefliger
Add a compatible for the HP EliteBook Ultra G1q 14 inch Notebook AI PC. The laptop is based on the Snapdragon X Elite (x1e80100) SoC. PDF link: http://www8.hp.com/h20195/v2/GetDocument.aspx?docname=c08996392 Signed-off-by: Juerg Haefliger <juerg.haefliger@canonical.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250429144957.2088284-3-juerg.haefliger@canonical.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018George Moussalem
Document the qcom,tcsr-ipq5018 compatible. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250512-ipq5018-syscon-v1-1-eb1ad2414c3c@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14dt-bindings: cache: add QiLai compatible to ax45mpBen Zong-You Xie
Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for qilai-ax45mp-cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-05-14dt-bindings: gpio: tegra186: Add gpio-rangesAaron Kling
Add optional gpio-ranges property. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250429-tegra186-pinctrl-v1-2-722c7c42394e@gmail.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-05-14dt-bindings: mmc: vt8500-sdmmc: Convert to YAMLAlexey Charkov
Rewrite the textual description for the WonderMedia SDMMC controller as YAML schema, and switch the filename to follow the compatible string. Signed-off-by: Alexey Charkov <alchark@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250423-vt8500-sdmmc-binding-v2-1-ea4f17fd0638@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: sdhci-msm: Add the SM7150 compatibleDanila Tikhonov
Add compatible for the SDHCI block found in SM7150. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-11-bf9a9081631d@jiaxyga.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: fsl,esdhc: add compatible string fsl,ls1021a-esdhcFrank Li
Add compatible string fsl,ls1021a-esdhc for LS1021a SoC. Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250417151300.3570021-1-Frank.Li@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: mtk-sd: Add support for Dimensity 1200 MT6893AngeloGioacchino Del Regno
Add a compatible for the MediaTek Dimensity 1200 (MT6893) SoC. All of the MMC/SD controllers in this chip are compatible with the ones found in MT8183, but do also make use of an optional crypto clock when enabling HW disk encryption. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120245.147951-1-angelogioacchino.delregno@collabora.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2044 supportInochi Amaoto
The sdhci IP of SG2044 is similar to it of SG2042. They share the same clock and controller configuration. Add compatible string for SG2044. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250413223507.46480-8-inochiama@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: arasan,sdhci: Add Renesas RZ/N1DWolfram Sang
This instance has a wakeup irq defined. It is currently not used by the driver. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250405173631.13564-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: renesas,sdhi: Document RZ/V2N supportLad Prabhakar
Add SDHI bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. Use `renesas,sdhi-r9a09g057` as a fallback since the SD/MMC block on RZ/V2N is identical to the one on RZ/V2H(P), allowing reuse of the existing driver without modifications. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250326143945.82142-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: marvell,xenon-sdhci: Drop requiring 2 clocksRob Herring (Arm)
The "axi" clock is optional on at least the "marvell,armada-ap806-sdhci" variant. Not sure what's correct here, so just drop the constraint. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250320-dt-marvell-mmc-v1-3-e51002ea0238@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: marvell,xenon-sdhci: Add reference to sdhci-common.yamlRob Herring (Arm)
The Marvell xenon-sdhci block is an SDHCI and can use properties from sdhci-common.yaml, so change the reference. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250320-dt-marvell-mmc-v1-2-e51002ea0238@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: marvell,xenon-sdhci: Allow "dma-coherent" and "iommus"Rob Herring (Arm)
The Marvell xenon-sdhci block can be cache-coherent and needs the "dma-coherent" property. It can also be behind an IOMMU and needs the "iommus" property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250320-dt-marvell-mmc-v1-1-e51002ea0238@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: Remove redundant sdhci.txtRob Herring (Arm)
The properties in sdhci.txt are documented in sdhci-common.yaml, too. Remove the txt binding. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250320211922.1135669-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCsFabrizio Castro
Document the Renesas RZ/V2H(P) family of SoCs DMAC block. The Renesas RZ/V2H(P) DMAC is very similar to the one found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250423143422.3747702-3-fabrizio.castro.jz@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1HFabrizio Castro
Make sure we don't allow for the clocks, clock-names, resets, reset-names. and power-domains properties for the Renesas RZ/A1H SoC because its DMAC doesn't have clocks, resets, and power domains. Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250423143422.3747702-2-fabrizio.castro.jz@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: Document Tegra264 ADMA supportSheetal
Add Tegra264 ADMA support to the device tree bindings documentation. The Tegra264 ADMA hardware supports 64 DMA channels and requires specific register configurations. Signed-off-by: Sheetal <sheetal@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250512050010.1025259-2-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14ASoC: dt-bindings: mediatek: Simplify mediatek,clk-providerKrzysztof Kozlowski
"mediatek,clk-provider" property is a string, not an string array, thus "items" is not really correct. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250514105702.28622-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14regulator: dt-bindings: mt6357: Drop fixed compatible requirementNícolas F. R. A. Prado
Some of the regulators on the MT6357 PMIC currently reference the fixed-regulator dt-binding, which enforces the presence of a regulator-fixed compatible. However since all regulators on the MT6357 PMIC are handled by a single mt6357-regulator driver, probed through MFD, the compatibles don't serve any purpose. In fact they cause failures in the DT kselftest since they aren't probed by the fixed regulator driver as would be expected. Furthermore this is the only dt-binding in this family like this: mt6359-regulator and mt6358-regulator don't require those compatibles. Commit d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles") removed the compatibles from Devicetree, but missed updating the binding, which still requires them, introducing dt-binding errors. Remove the compatible requirement by referencing the plain regulator dt-binding instead to fix the dt-binding errors. Fixes: d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://patch.msgid.link/20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14dt-bindings: phy: rockchip,inno-usb2phy: add rk3562Kever Yang
Add compatible for the USB2 phy in the Rockchip RK3562 SoC. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatibleHeiko Stuebner
Add compatible for the USB2 phy in the Rockchip RK3036 SoC. Apart from some bits that got swapped around in the phy registers, the block is nearly the same as the one on the rk3128. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoCLad Prabhakar
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC. RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it needs additional configuration to be done as compared RZ/G2L USB2.0 phy. To handle this difference a SoC specific compat string is added for RZ/V2H(P) SoC. Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets` property and has two clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L familyLad Prabhakar
The RZ/G2L family requires two clocks for USB2 PHY, which are already defined in the DTSI files. Add a constraint in the DT binding document to ensure validation with `dtbs_check`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 supportIvaylo Ivanov
Document support for Exynos2200. As the USBDRD 3.2 4nm controller consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will be handled by external drivers, define only the bus clocked used by the link controller. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: add exynos2200 eusb2 phy supportIvaylo Ivanov
Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, the driver doesn't make use of reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schemaRob Herring (Arm)
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the example to the GRF binding as that has the complete block. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: imx8mq-usb: add imx95 tuning supportXu Yang
The parameter value of below 3 properties are USB PHY specific. i.MX8MP and i.MX95 USB PHY has different meanings. This will enlarge parameters value and add constraints for them. - fsl,phy-tx-vref-tune-percent - fsl,phy-tx-rise-tune-percent - fsl,phy-comp-dis-tune-percent Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt propertyXu Yang
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in register PHY_CTRL3 bit[31:29]. 011: Corresponds to a launch amplitude of 1.12 V. 010: Corresponds to a launch amplitude of 1.04 V. 000: Corresponds to a launch amplitude of 0.88 V. After updated: 011: Corresponds to a launch amplitude of 0.844 V. 100: Corresponds to a launch amplitude of 1.008 V. 101: Corresponds to a launch amplitude of 1.156 V. This will correct it accordingly. Fixes: b2e75563dc39 ("dt-bindings: phy: imx8mq-usb: add phy tuning properties") Cc: stable@vger.kernel.org Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14ASoC: dt-bindings: Add Everest ES8389 audio CODECZhang Yi
Add device tree binding documentation for Everest ES8389 which is different from ES8388 Signed-off-by: Zhang Yi <zhangyi@everest-semi.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250514094546.35508-3-zhangyi@everest-semi.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14dt-bindings: phy: mediatek,tphy: Add support for MT6893AngeloGioacchino Del Regno
Add a compatible string for the MediaTek Dimensity 1200 (MT6893) SoC: this chip integrates a MediaTek generic T-PHY version 2. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893AngeloGioacchino Del Regno
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI PHY found in this chip is fully compatible with the one found in the MT8183 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: arm: stm32: Document Ultratronik's Fly board DT bindingGoran Rađenović
This commit documents ultra-fly-sbc devicetree binding based on STM32MP157 SoC. Signed-off-by: Goran Rađenović <goran.radni@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250508143818.2574558-3-goran.radni@gmail.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: vendor-prefixes: Add UltratronikGoran Rađenović
Ultratronik GmbH is a German electronics company: https://www.ultratronik-ems.de/ Signed-off-by: Goran Rađenović <goran.radni@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250508143818.2574558-2-goran.radni@gmail.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: arm: stm32: add compatible for stm32h747i-disco boardDario Binacchi
The board includes an STM32H747XI SoC with the following resources: - 2 Mbytes Flash - 1 MByte SRAM - LCD-TFT controller - MIPI-DSI interface - FD-CAN - USB 2.0 high-speed/full-speed - Ethernet MAC - camera interface Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250427074404.3278732-3-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schemaRob Herring (Arm)
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the missing "power-domains" property and "port" and "orientation-switch" properties in the child nodes. Omit the previously deprecated properties as they aren't used anywhere. Drop the 2nd example which was pretty much identical to the 1st example. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMIISiddharth Vadapalli
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value of "12" while the existing maximum allowed PHY TYPE is "9", switch back to using "enum" property in the bindings to account for this discontinuity. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mtk-xs-phy: support type switch by pericfgFrank Wunderlich
Add support for type switch by pericfg register between USB3/PCIe. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mtk-xs-phy: Add mt7988 compatibleFrank Wunderlich
Add compatible for xs-phy on mt7988. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: ata: Convert ti,dm816-ahci to DT schemaRob Herring (Arm)
Convert the TI DM816 AHCI SATA Controller to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display ControllerLiu Ying
i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-9-victor.liu@nxp.com
2025-05-14dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt ↵Liu Ying
controller i.MX8qxp Display Controller has a built-in interrupt controller to support Enable/Status/Preset/Clear interrupt bit. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-8-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencerLiu Ying
i.MX8qxp Display Controller contains a command sequencer is designed to autonomously process command lists. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-7-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance ↵Liu Ying
counter i.MX8qxp Display Controller contains a AXI performance counter which allows measurement of average bandwidth and latency during operation. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-6-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engineLiu Ying
i.MX8qxp Display Controller pixel engine consists of all processing units that operate in the AXI bus clock domain. Command sequencer and interrupt controller of the Display Controller work with AXI bus clock, but they are not in pixel engine. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-5-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller display engineLiu Ying
i.MX8qxp Display Controller display engine consists of all processing units that operate in a display clock domain. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-4-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engineLiu Ying
i.MX8qxp Display Controller contains a blit engine for raster graphics. It may read up to 3 source images from memory and computes one destination image from it, which is written back to memory. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-3-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller processing unitsLiu Ying
Freescale i.MX8qxp Display Controller is implemented as construction set of building blocks with unified concept and standardized interfaces. Document all existing processing units. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-2-victor.liu@nxp.com
2025-05-13dt-bindings: trivial-devices: Add Maxim max30208Rodrigo Gobbi
The temperature sensor for maxim is a simple i2c driver, it's eligible to trivial devices. Signed-off-by: Rodrigo Gobbi <rodrigo.gobbi.7@gmail.com> Link: https://lore.kernel.org/r/20250503190509.33074-1-rodrigo.gobbi.7@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml referenceRob Herring (Arm)
The reserved-memory.yaml reference needs the full path. No warnings were generated because the example has the wrong compatible string, so fix that too. Fixes: 304a90c4f75d ("dt-bindings: soc: fsl: Convert q(b)man-* to yaml format") Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250507154231.1590634-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-22 15:30:01 +0000