Age | Commit message (Collapse) | Author | |
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2018-12-06 | Documentation: perf: Add documentation for ThunderX2 PMU uncore driver | Kulkarni, Ganapatrao | |
The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> [will: minor spelling and format fixes, dropped events list] Signed-off-by: Will Deacon <will.deacon@arm.com> |