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2024-12-11coresight: dummy: Add static trace id support for dummy sourceMao Jinlong
Some dummy source has static trace id configured in HW and it cannot be changed via software programming. Configure the trace id in device tree and reserve the id when device probe. Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Link: https://lore.kernel.org/r/20241121062829.11571-4-quic_jinlmao@quicinc.com [ Fix Date and Version to December 2024, v6.14 ] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
2024-12-11dt-bindings: arm: Add arm,static-trace-id for coresight dummy sourceMao Jinlong
Some dummy source HW has static trace id which cannot be changed via software programming. Add arm,static-trace-id for static id support to coresight dummy source. Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20241121062829.11571-2-quic_jinlmao@quicinc.com
2024-12-11dt-bindings: soc: amlogic,meson-gx-hhi-sysctrl: Document the System Control ↵Neil Armstrong
registers found on early Meson SoC The early Amlogic SoCs also has a System Control registers register set, document it in the amlogic,meson-gx-hhi-sysctrl now the clock controller has been converted to yaml dt-schema. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20241007-topic-amlogic-arm32-upstream-bindings-fixes-hhi-sysctrl-meson8-v1-1-896b24e6c3c8@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-12-10Documentation: networking: Add a caveat to nexthop_compat_mode sysctlPetr Machata
net.ipv4.nexthop_compat_mode was added when nexthop objects were added to provide the view of nexthop objects through the usual lens of the route UAPI. As nexthop objects evolved, the information provided through this lens became incomplete. For example, details of resilient nexthop groups are obviously omitted. Now that 16-bit nexthop group weights are a thing, the 8-bit UAPI cannot convey the >8-bit weight accurately. Instead of inventing workarounds for an obsolete interface, just document the expectations of inaccuracy. Fixes: b72a6a7ab957 ("net: nexthop: Increase weight to u16") Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: David Ahern <dsahern@kernel.org> Link: https://patch.msgid.link/b575e32399ccacd09079b2a218255164535123bd.1733740749.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-10dt-bindings: display: rockchip: Add schema for RK3588 DW DSI2 controllerHeiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication protocols defined by the MIPI Alliance. The RK3588 implements this specification in its two MIPI DSI-2 Host Controllers that are based on a new Synopsys IP. Tested-by: Dmitry Yashin <dmt.yashin@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20241209231021.2180582-3-heiko@sntech.de
2024-12-10dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generatorClaudiu Beznea
There are some differences b/w 5L35023 and 5P35023 Versa3 clock generator variants but the same driver could be used with minimal adjustments. The identified differences are PLL2 Fvco, the clock sel bit for SE2 clock and different default values for some registers. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20241210170953.2936724-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-12-10Documentation: PM: Clarify pm_runtime_resume_and_get() return valuePaul Barker
Update the documentation to match the behaviour of the code. pm_runtime_resume_and_get() always returns 0 on success, even if __pm_runtime_resume() returns 1. Fixes: 2c412337cfe6 ("PM: runtime: Add documentation for pm_runtime_resume_and_get()") Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Link: https://patch.msgid.link/20241203143729.478-1-paul.barker.ct@bp.renesas.com [ rjw: Subject and changelog edits, adjusted new comment formatting ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-12-10Merge branch 'linus' into x86/cleanups, to resolve conflictIngo Molnar
These two commits interact: upstream: 73da582a476e ("x86/cpu/topology: Remove limit of CPUs due to disabled IO/APIC") x86/cleanups: 13148e22c151 ("x86/apic: Remove "disablelapic" cmdline option") Resolve it. Conflicts: arch/x86/kernel/cpu/topology.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2024-12-10Documentation: Merge x86-specific boot options doc into kernel-parameters.txtBorislav Petkov (AMD)
Documentation/arch/x86/x86_64/boot-options.rst is causing unnecessary confusion by being a second place where one can put x86 boot options. Move them into the main one. Drop removed ones like "acpi=ht", while at it. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Link: https://lore.kernel.org/r/20241202190011.11979-1-bp@kernel.org
2024-12-10Documentation: Add documentation about class interface for platform profilesMario Limonciello
The class interface allows changing multiple platform profiles on a system to different values. The semantics of it are similar to the legacy interface. Reviewed-by: Armin Wolf <W_Armin@gmx.de> Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Reviewed-by: Mark Pearson <mpearson-lenovo@squebb.ca> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20241206031918.1537-23-mario.limonciello@amd.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2024-12-10cpufreq/amd-pstate: Store the boost numerator as highest perf againMario Limonciello
commit ad4caad58d91d ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()") changed the semantics for highest perf and commit 18d9b52271213 ("cpufreq/amd-pstate: Use nominal perf for limits when boost is disabled") worked around those semantic changes. This however is a confusing result and furthermore makes it awkward to change frequency limits and boost due to the scaling differences. Restore the boost numerator to highest perf again. Suggested-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Fixes: ad4caad58d91 ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()") Link: https://lore.kernel.org/r/20241209185248.16301-2-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
2024-12-10drivers/perf: hisi: Export associated CPUs of each PMU through sysfsYicong Yang
Although the event of the uncore PMU can only be opened on a single CPU, some PMU does have the affinity on a range of CPUs. For example the L3C PMU is associated to the CPUs sharing the L3T it monitors. Users may infer this affinity by the PMU name which may have SCCL ID and CCL ID encoded (for L3C etc), but it's not that straightforward. So export this information by adding an "associated_cpus" sysfs attribute then user can get this directly. Reviewed-by: Jonathan Cameron <Joanthan.Cameron@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20241210141525.37788-9-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-10dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschemaNeil Armstrong
Convert the Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller bindings to dt-schema. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-5-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: document mmc-slotNeil Armstrong
Document the mmc-slot, which is a subnode of a multi-slot MMC controller, each slot is represented as a full MMC controller, the top node handling all the shared resources and slot mux. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-4-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: controller: remove '|' when not neededNeil Armstrong
Adding "|" is used to keep the description format, remove it when not needed after the split into mmc-controller.yaml and mmc-controller-common.yaml files. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-3-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: controller: move properties common with slot out to ↵Neil Armstrong
mmc-controller-common Move the common MMC "slot" properties because they are shared by the single-slot or multi-slot controllers, and will help defining a simple mmc-slot bindings document with proper slot properties and nodename. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-2-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: controller: clarify the address-cells descriptionNeil Armstrong
The term "slot ID" has nothing to do with the SDIO function number which is specified in the reg property of the subnodes, rephrase the description to be more accurate. Fixes: f9b7989859dd ("dt-bindings: mmc: Add YAML schemas for the generic MMC options") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-1-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: power: domain-idle-state: Allow idle-state-nameKonrad Dybcio
Allow specifying a name for idle states, similar to CPU idle states in cpu/idle-states.yaml Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Message-ID: <20241130-topic-idle_state_name-v1-1-d0ff67b0c8e9@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: soc: renesas: Document R8A779G3 White Hawk SingleGeert Uytterhoeven
Document the compatible value for the Renesas R-Car V4H ES3.0 (R8A779G3) SoC, as used on the Renesas White Hawk Single board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/1d2d2a6cbf31c817f574f6eed310a960e6175afe.1733156661.git.geert+renesas@glider.be
2024-12-10dt-bindings: soc: renesas: Move R8A779G0 White Hawk upGeert Uytterhoeven
Move the R8A779G0-only White Hawk board stack section up, just below the R8A779G0-only White Hawk CPU section, to improve sort order. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/d553ef4b1f969f72e384f274d42ac7a62fe45fd4.1733156661.git.geert+renesas@glider.be
2024-12-10dt-bindings: Drop Bhupesh Sharma from maintainersKrzysztof Kozlowski
For more than a year all emails to Bhupesh Sharma's Linaro emails bounce and there were no updates to mailmap. No reviews from Bhupesh, either, so change the maintainer to Bjorn and Konrad (Qualcomm SoC maintainers). Cc: Bhupesh Sharma <bhupesh.linux@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Konrad Dybcio <konradybcio@kernel.org> Message-ID: <20241130094758.15553-1-krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: atmel,sama5d2-sdhci: add microchip,sama7d65-sdhciDharma Balasubiramani
Add mmc binding documentation for SAMA7D65. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Message-ID: <e9e9e4cf0753422706bdc44fe7d20ca3a686ce7a.1732030972.git.Ryan.Wanner@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: mmc: marvell,xenon-sdhci: Simplify Armada 3700 if/then schemaRob Herring (Arm)
Properties are supposed to be defined in the top-level schema and then disallowed in an if/then schema if necessary. Move the "marvell,pad-type" property to follow this. "reg" can also be similarly described at the top-level with only the number of entries restricted in the if/then schema. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Message-ID: <20241113225602.1782573-1-robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-12-10dt-bindings: arm: stm32: add compatible strings for Linux Automation LXA TAC ↵Leonard Göhrs
gen 3 The Linux Automation LXA TAC generation 3 is built around an OSD32MP153x SiP with CPU, RAM, PMIC, Oscillator and EEPROM. LXA TACs are a development tool for embedded devices with a focus on embedded Linux devices. Add compatible for the generation 3 based on the STM32MP153c. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10dt-bindings: crypto: qcom-qce: document the QCS8300 crypto engineYuvaraj Ranganathan
Document the crypto engine on the QCS8300 Platform. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-12-10dt-bindings: crypto: ice: document the qcs8300 inline crypto engineYuvaraj Ranganathan
Add the compatible string for QCom ICE on qcs8300 SoCs. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-12-10dt-bindings: crypto: qcom,prng: document QCS8300Yuvaraj Ranganathan
Document QCS8300 compatible for the True Random Number Generator. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-12-09scsi: Eliminate scsi_register() and scsi_unregister() usage & docsRandy Dunlap
scsi_mid_low_api.rst refers to scsi_register() and scsi_unregister() but these functions don't exist. They have been replaced by more meaningful names. Update one driver (megaraid_mbox.c) that uses "scsi_unregister" in a warning message. Update scsi_mid_low_api.rst to eliminate references to scsi_register() and scsi_unregister(). Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20241205041839.164404-1-rdunlap@infradead.org Cc: James E.J. Bottomley <James.Bottomley@HansenPartnership.com> Cc: Martin K. Petersen <martin.petersen@oracle.com> Cc: Bart Van Assche <bvanassche@acm.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-doc@vger.kernel.org Cc: Kashyap Desai <kashyap.desai@broadcom.com> Cc: Sumit Saxena <sumit.saxena@broadcom.com> Cc: Shivasharan S <shivasharan.srikanteshwara@broadcom.com> Cc: Chandrakanth patil <chandrakanth.patil@broadcom.com> Cc: megaraidlinux.pdl@broadcom.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2024-12-09scsi: docs: Remove init_this_scsi_driver()Randy Dunlap
Finish removing mention of init_this_scsi_driver() that was removed ages ago. Fixes: 83c9f08e6c6a ("scsi: remove the old scsi_module.c initialization model") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20241205031307.130441-1-rdunlap@infradead.org Cc: Christoph Hellwig <hch@lst.de> Cc: Martin K. Petersen <martin.petersen@oracle.com> Cc: James E.J. Bottomley <James.Bottomley@HansenPartnership.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-doc@vger.kernel.org Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2024-12-09dt-bindings: net: Add DT bindings for DWMAC on NXP S32G/R SoCsJan Petrous (OSS)
Add basic description for DWMAC ethernet IP on NXP S32G2xx, S32G3xx and S32R45 automotive series SoCs. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Link: https://patch.msgid.link/20241205-upstream_s32cc_gmac-v8-13-ec1d180df815@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-09dt-bindings: arm: samsung: samsung-boards: Add bindings for SM-G981B and ↵Umer Uddin
SM-G980F board Add devicetree bindings for Samsung Galaxy S20 5G and Samsung Galaxy S20 board. Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209080059.11891-2-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09dt-bindings: arm-smmu: Document SM8750 SMMUMelody Olvera
Document the SM8750 SMMU block. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_smmu-v2-1-9e73e3fc15f2@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09dt-bindings: arm-smmu: document QCS615 GPU SMMUQingqing Zhou
Add the compatible for Qualcomm QCS615 GPU SMMU. Add the compatible in the list of 3 clocks required by the GPU SMMU. Remove the compatible from the "no clocks" list. Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241122074922.28153-2-quic_qqzhou@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09dt-bindings: iommu: arm,smmu: add sdm670 adreno iommu compatibleRichard Acayan
SDM670 has a separate IOMMU for the GPU, like SDM845. Add the compatible for it. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241114004713.42404-5-mailingradian@gmail.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09Merge tag 'sched_urgent_for_v6.13_rc3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler fixes from Borislav Petkov: - Remove wrong enqueueing of a task for a later wakeup when a task blocks on a RT mutex - Do not setup a new deadline entity on a boosted task as that has happened already - Update preempt= kernel command line param - Prevent needless softirqd wakeups in the idle task's context - Detect the case where the idle load balancer CPU becomes busy and avoid unnecessary load balancing invocation - Remove an unnecessary load balancing need_resched() call in nohz_csd_func() - Allow for raising of SCHED_SOFTIRQ softirq type on RT but retain the warning to catch any other cases - Remove a wrong warning when a cpuset update makes the task affinity no longer a subset of the cpuset * tag 'sched_urgent_for_v6.13_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: locking: rtmutex: Fix wake_q logic in task_blocks_on_rt_mutex sched/deadline: Fix warning in migrate_enable for boosted tasks sched/core: Update kernel boot parameters for LAZY preempt. sched/core: Prevent wakeup of ksoftirqd during idle load balance sched/fair: Check idle_cpu() before need_resched() to detect ilb CPU turning busy sched/core: Remove the unnecessary need_resched() check in nohz_csd_func() softirq: Allow raising SCHED_SOFTIRQ from SMP-call-function on RT kernel sched: fix warning in sched_setaffinity sched/deadline: Fix replenish_dl_new_period dl_server condition
2024-12-09perf/marvell: Odyssey LLC-TAD performance monitor supportGowthami Thiagarajan
Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc. Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance: perf stat -e tad_hit_ltg,tad_hit_dtg <workload> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-6-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09perf/marvell: Odyssey DDR Performance monitor supportGowthami Thiagarajan
Odyssey DRAM Subsystem supports eight counters for monitoring performance and software can program those counters to monitor any of the defined performance events. Supported performance events include those counted at the interface between the DDR controller and the PHY, interface between the DDR Controller and the CHI interconnect, or within the DDR Controller. Additionally DSS also supports two fixed performance event counters, one for ddr reads and the other for ddr writes. Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-4-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09Documentation: dwc_pcie_pmu: Fix the mnemonics and eventidIlkka Koskinen
Fix the event id and type in the example. In addition, the recent fix, which addressed the mnemonics with mixed case, didn't fix the document. Match the names with the driver. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com> Link: https://lore.kernel.org/r/20241205061914.5568-3-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09Merge remote-tracking branch 'drm/drm-next' into drm-misc-nextMaarten Lankhorst
The v6.13-rc2 release included a bunch of breaking changes, specifically the MODULE_IMPORT_NS commit. Backmerge in order to fix them before the next pull-request. Include the fix from Stephen Roswell. Caused by commit 25c3fd1183c0 ("drm/virtio: Add a helper to map and note the dma addrs and lengths") Interacting with commit cdd30ebb1b9f ("module: Convert symbol namespace to string literal") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Link: https://patchwork.freedesktop.org/patch/msgid/20241209121717.2abe8026@canb.auug.org.au Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2024-12-09perf: arm_cspmu: nvidia: monitor all ports by defaultBesar Wicaksono
Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide port filtering. If the port filter is set to zero, the counter of these PMUs will not capture any event. To avoid meaningless experiment, the driver sets the port filter value to a default non-zero value. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-5-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09perf: arm_cspmu: nvidia: enable NVLINK-C2C port filteringBesar Wicaksono
Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-4-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09perf: arm_cspmu: nvidia: fix sysfs path in the kernel docBesar Wicaksono
Fix typos to the sysfs path referenced by NVIDIA uncore pmu kernel doc. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-3-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
2024-12-09Merge drm/drm-next into drm-xe-nextRodrigo Vivi
Catch up with -rc2 and fixing namespace conflict issue caused by commit cdd30ebb1b9f ("module: Convert symbol namespace to string literal") and commit 0c45e76fcc62 ("drm/xe/vsec: Support BMG devices") Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-12-09regulator: dt-bindings: pca9450: Add pca9452 supportJoy Zou
Add compatible string 'nxp,pca9452'. pca9452 add 'ldo3' compared with pca9451a. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20241205-pca9450-v1-3-aab448b74e78@nxp.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09regulator: dt-bindings: qcom,qca6390-pmu: document wcn6750-pmuJanaki Ramaiah Thota
Add description of the PMU node for the WCN6750B module. Signed-off-by: Janaki Ramaiah Thota <quic_janathot@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20241209103455.9675-2-quic_janathot@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: Merge up v6.12-rc2Mark Brown
This has fixes for several boards which help my testing a lot.
2024-12-09ASoC: Merge up v6.12-rc2Mark Brown
This has fixes for several boards which help my testing a lot.
2024-12-09dt-bindings: arm: mediatek: Add MT8186 Starmie ChromebooksWojciech Macek
Add an entry for the MT8186 based Starmie Chromebooks, also known as the ASUS Chromebook Enterprise CM30 Detachable (CM3001). The device is a tablet style chromebook. Signed-off-by: Wojciech Macek <wmacek@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241129055720.3328681-2-wmacek@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09dt-bindings: arm: mediatek: Add MT8188 Lenovo Chromebook Duet (11", 9)Fei Shao
Add entries for the MT8188-based Chromebook "Ciri", also known as Lenovo Chromebook Duet (11", 9). This device features a detachable design with touchscreen, detachable keyboard and USI 2.0 Stylus support, and has 8 SKUs to accommodate the combinations of second-source components. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241124085739.290556-2-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09livepatch: Add stack_order sysfs attributeWardenjohn
Add "stack_order" sysfs attribute which holds the order in which a live patch module was loaded into the system. A user can then determine an active live patched version of a function. cat /sys/kernel/livepatch/livepatch_1/stack_order -> 1 means that livepatch_1 is the first live patch applied cat /sys/kernel/livepatch/livepatch_module/stack_order -> N means that livepatch_module is the Nth live patch applied Suggested-by: Petr Mladek <pmladek@suse.com> Suggested-by: Miroslav Benes <mbenes@suse.cz> Suggested-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Wardenjohn <zhangwarden@gmail.com> Acked-by: Josh Poimboeuf <jpoimboe@kernel.org> Reviewed-by: Petr Mladek <pmladek@suse.com> Tested-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Miroslav Benes <mbenes@suse.cz> Link: https://lore.kernel.org/r/20241008014856.3729-2-zhangwarden@gmail.com [pmladek@suse.com: Updated kernel version and date in the ABI documentation.] Signed-off-by: Petr Mladek <pmladek@suse.com>
generated by cgit (git 2.34.1) at 2025-09-22 22:43:05 +0000