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2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2022-11-28ARM: dts: armada-xp: add interrupts for watchdogChris Packham
The first interrupt is for the regular watchdog timeout. Normally the RSTOUT line will trigger a reset before this interrupt fires but on systems with a non-standard reset it may still trigger. The second interrupt is for a timer1 which is used as a pre-timeout for the watchdog. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2022-09-02ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for PCIe legacy INTx ↵Pali Rohár
interrupts Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-29ARM: dts: Add i2c0 pinctrl information for 98dx3236Chris Packham
Add pinctrl information for the 98dx3236 (and variants). There is only one choice for i2c0 MPP14 and MPP15. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-29ARM: dts: Remove non-existent i2c1 from 98dx3236Chris Packham
The switches with integrated CPUs have only got a single i2c controller. They incorrectly gained one when they were split from the Armada-XP. Fixes: 43e28ba87708 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236") Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-08ARM: dts: armada-xp: add label to sdram-controller nodeChris Packham
Add the label "sdramc" to the sdram-controller nodes for the Armada-XP and 98dx3236 SoCs. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-27ARM: dts: armada-xp-98dx3236: Switch to armada-38x-uart serial nodeJoshua Scott
Switch to the "marvell,armada-38x-uart" driver variant to empty the UART buffer before writing to the UART_LCR register. Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Tested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>. Cc: stable@vger.kernel.org Fixes: 43e28ba87708 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-21ARM: dts: mvebu: add "marvell,prestera" to PP nodesChris Packham
The compatible string "marvell,prestera" allows drivers to have code common to any prestera variant. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-20ARM: dts: mvebu: 98dx3236: Rename nand controller nodeChris Packham
Update the 98dx3236 SoC and dependent boards to use "nand-controller" instead of "nand". Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-18ARM: dts: armada-xp-98dx: Add NAND pinctrl informationChris Packham
Add pin control information for the NAND interface on the Armada 98DX3236 and variants. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-27arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCsGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2017-08-03ARM: dts: marvell: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17ARM: dts: mvebu: disable the rtc on 98dx3236 SoCChris Packham
There is no rtc for the 98dx3236 and derivative SoCs. Disable the rtc node inherited from the armada-370-xp base. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236Chris Packham
The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port 0.1 MEM" range was errantly kept when creating a specific dts for the SoC. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08ARM: dts: mvebu: Move mv98dx3236 clock bindingsChris Packham
Previously the coreclk binding for the 98dx3236 SoC was inherited from the armada-370/xp. This block is present in as much as it is possible to read from the register location without causing any harm. However the actual sampled at reset values are reflected in the DFX block. Moving the binding to the DFX block enables support for different clock strapping options in hardware. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236Chris Packham
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In reality there are a number of differences to the actual Armada-XP so rather than including armada-xp.dtsi and disabling many of the IP blocks. Include armada-370-xp.dtsi and add the required nodes. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08ARM: dts: armada-xp-98dx3236: combine dfx server nodesChris Packham
Rather than having a separate node for the dfx server add a reg property to the parent node. This give some compatibility with the Marvell supplied SDK. As no upstream driver currently exists for this block and support for this SoC is still quite fresh in the kernel it should not be necessary to retain a backwards compatible binding. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-31ARM: dts: mvebu: Add device tree for 98DX3236 SoCsChris Packham
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. [gregory.clement@free-electrons.com: fix topic] Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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