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2020-06-29ARM: dts: meson: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski
Fix dtschema validator warnings like: l2-cache-controller@c4200000: $nodename:0: 'l2-cache-controller@c4200000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200626080626.4080-1-krzk@kernel.org
2020-05-19ARM: dts: meson: add the gadget mode properties to the USB0 controllerMartin Blumenstingl
Testing with a USB RNDIS connection and iperf3 gives the following results: - From the host computer to the device at ~250Mbit/s - From the device to the host computer at ~76Mbit/s Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200504195105.2909711-1-martin.blumenstingl@googlemail.com
2019-12-11ARM: dts: meson: provide the XTAL clock using a fixed-clockMartin Blumenstingl
The clock controller driver has provided the XTAL clock so far. This does not match how the hardware actually works because the XTAL clock is an actual crystal which is mounted on the PCB. Add the "xtal" clock to meson.dtsi and replace all references to the clock controller's CLKID_XTAL with the new xtal clock node. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-03ARM: dts: meson: update with SPDX Licence identifierNeil Armstrong
While the text specifies "of the GPL or the X11 license" the actual license text matches the MIT license as specified at [0] [0] https://spdx.org/licenses/MIT.html Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16ARM: dts: meson: add support for the RTCMartin Blumenstingl
The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The RTC requires an external 32.768 kHz oscillator to work properly. Whether or not this crystal exists depends on the board, so it has to be added for each board.dts (instead of adding it somewhere in a generic .dtsi). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-06Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC device tree updates from Arnd Bergmann: "This is a smaller update than the past few times, but with just over 500 non-merge changesets still dwarfes the rest of the SoC tree. Three new SoC platforms get added, each one a follow-up to an existing product, and added here in combination with a reference platform: - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor: https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics Applications": https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X These are actual commercial products we now support with an in-kernel device tree source file: - Bosch Guardian is a product made by Bosch Power Tools GmbH, based on the Texas Instruments AM335x chip - Winterland IceBoard is a Texas Instruments AM3874 based machine used in telescopes at the south pole and elsewhere, see commit d031773169df2 for some pointers: - Inspur on5263m5 is an x86 server platform with an Aspeed ast2500 baseboard management controller. This is for running on the BMC. - Zodiac Digital Tapping Unit, apparently a kind of ethernet switch used in airplanes. - Phicomm K3 is a WiFi router based on Broadcom bcm47094 - Methode Electronics uDPU FTTdp distribution point unit - X96 Max, a generic TV box based on Amlogic G12a (S905X2) - NVIDIA Shield TV (Darcy) based on Tegra210 And then there are several new SBC, evaluation, development or modular systems that we add: - Three new Rockchips rk3399 based boards: - FriendlyElec NanoPC-T4 and NanoPi M4 - Radxa ROCK Pi 4 - Five new i.MX6 family SoM modules and boards for industrial products: - Logic PD i.MX6QD SoM and evaluation baseboad - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357 microcontroller - Chameleon96, an Intel/Altera Cyclone5 based FPGA development system in 96boards form factor - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual platform for corresponding to the latest "fast model" - Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit and 64-bit mode. - Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards enterprise form factor - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108 For already supported boards and SoCs, we often add support for new devices after merging the drivers. This time, the largest changes include updates for - STMicroelectronics stm32mp1, which was now formally launched last week - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip - Action Semi S700 - TI AM654x, their recently merged 64-bit SoC from the OMAP family - Various Amlogic Meson SoCs - Mediatek MT2712 - NVIDIA Tegra186 and Tegra210 - The ancient NXP lpc32xx family - Samsung s5pv210, used in some older mobile phones Many other chips see smaller updates and bugfixes beyond that" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits) ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4 dt-bindings: net: ti: deprecate cpsw-phy-sel bindings ARM: dts: am335x: switch to use phy-gmii-sel ARM: dts: am4372: switch to use phy-gmii-sel ARM: dts: dm814x: switch to use phy-gmii-sel ARM: dts: dra7: switch to use phy-gmii-sel arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference ARM: dts: exynos: Add support for secondary DAI to Odroid XU4 ARM: dts: exynos: Add support for secondary DAI to Odroid XU3 ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite ARM: dts: exynos: Add stdout path property to Arndale board ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU ARM: dts: exynos: Enable ADC on Odroid HC1 arm64: dts: sprd: Remove wildcard compatible string arm64: dts: sprd: Add SC27XX fuel gauge device arm64: dts: sprd: Add SC2731 charger device arm64: dts: sprd: Add ADC calibration support arm64: dts: sprd: Remove PMIC INTC irq trigger type arm64: dts: rockchip: Enable tsadc device on rock960 ARM: dts: rockchip: add chosen node on veyron devices ...
2019-02-15Merge tag 'amlogic-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.1 - more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: ec100: add the GPIO line names ARM: dts: meson8b: ec100: improve the description of the regulators ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature ARM: dts: meson8b: add the temperature calibration data for the SAR ADC ARM: dts: meson8: add the temperature calibration data for the SAR ADC ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible ARM: dts: meson: switch the clock controller to the HHI register area ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins ARM: dts: meson8b: add the Mali-450 MP2 GPU ARM: dts: meson8: add the Mali-450 MP6 GPU dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible ARM: dts: meson8b: add the APB bus ARM: dts: meson8: add the APB bus ARM: dts: meson6: add the APB2 bus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-11ARM: dts: meson: switch the clock controller to the HHI register areaMartin Blumenstingl
The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-01-10arm: dts: meson: Fix IRQ trigger type for macirqCarlo Caione
A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: 9c15795a4f96 ("ARM: dts: meson8b-odroidc1: ethernet support") Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripheralsMartin Blumenstingl
The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-28ARM: dts: meson: add the clock inputs for the Meson timerMartin Blumenstingl
The Meson Timer IP block has two clock inputs: - clk81 for using the system clock as timebase - xtal for a timebase with 1us, 10us, 100us and 1ms resolution The clocksource driver does not use these yet, but it's still a good idea to add them as this describes how the hardware actually works internally. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-28ARM: dts: meson: add the TIMER B/C/D interruptsMartin Blumenstingl
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events. For each of these a separate interrupt exists. Pass these interrupts to allow using the timers other than TIMER A. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-11-30ARM: dts: meson: fix the memory region of the GPIO interrupt controllerMartin Blumenstingl
commit 200a575b68d2 ("ARM: dts: meson: organize devices in their corresponding busses") organized all peripherals in busses so that the base register offset of the bus doesn't have to be included in all child-nodes anymore. The GPIO interrupt controller however specifies the register offset without subtracting the "cbus" base address. This leads to a problem where of_iomap inside the irq-meson-gpio driver fails because it actually tries to map 0x182209880 (cbus base = 0xc1100000 + 0xc1109880 for the GPIO interrupt controller). Fix this by using 0x9880 as register offset. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-11-30ARM: dts: meson: correct the sort order for the the gpio_intc nodeMartin Blumenstingl
Nodes are sorted by their register start address. Move gpio_intc to the correct position. No functional changes intended. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-29ARM: dts: meson: add the efuse nodeMartin Blumenstingl
Meson6, Meson8 and Meson8b use a similar IP block which has access to 512 bytes of efuse data. During SoC manufacturing some calibration settings for the CVBS connector and the internal temperature sensor are written to this efuse. On some boards it additionally stores for example the MAC addresses. The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6 since we do not have a clock driver there (which is required to read data from the efuse). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-29ARM: dts: meson8b: enable gpio interrupt controllerJerome Brunet
Add gpio interrupt controller node to the meson8b boards Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-11ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl
Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-06ARM: dts: meson: add SoC information nodesMartin Blumenstingl
The SoC type and version information is encoded in different register blocks. The SoC type information is part of the "assist" registers. The misc version information is part of the "bootrom" registers. On Meson8, Meson8b and Meson8m2 there is additionally information about the minor version. This information is stored in the "analog top" registers. Add the nodes for these register blocks so we can decode the SoC type and version information. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-06ARM: dts: meson: fixing USB support on Meson6, Meson8 and Meson8bEmiliano Ingrassia
This patch fixes the Meson6, Meson8 and Meson8b USB controllers dts nodes which interrupts are level type instead of edge type. This avoids errors like "usb 1-1-port1: cannot reset (err = -110)" and similars on Odroid-C1+ board. Fixes: e29b1cf87473 ("ARM: dts: meson: add USB support on Meson8 and Meson8b") Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-08-08ARM: dts: meson6: use stable UART bindingsNeil Armstrong
The UART bindings needs specifying a SoC family, use the meson6 family for the UART nodes like the other nodes. Switch to the stable UART bindings for meson6 by adding a XTAL node and using the proper compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-07-28ARM: dts: meson: add a node which describes the SRAMMartin Blumenstingl
All 32bit Meson SoCs contain 128KiB SRAM. This SRAM is used when suspending the device (the the ARM Power Firmware on Meson8/Meson8b/Meson8m2 saves the DDR settings there) and to boot the secondary CPU cores. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-07-28ARM: dts: move the pwm_ab and pwm_cd nodes to meson.dtsiMartin Blumenstingl
According to the vendor kernel sources these also exist (at the same address) on Meson6 and Meson8. This can be found by running $ grep -R "define PWM_PWM_[A-D]" arch/arm/ in the Amlogic GPL kernel tree (arm-src-kernel-2015-01-15-321cfb5a46). pwm_ef does not seem to exist on older SoCs, so we keep it in meson8b.dtsi for now. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16ARM: dts: meson: add USB support on Meson8 and Meson8bMartin Blumenstingl
This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16ARM: dts: meson: add the hardware random number generatorMartin Blumenstingl
All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16ARM: dts: meson: add the SAR ADCMartin Blumenstingl
This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macrosMartin Blumenstingl
This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-26ARM: dts: meson: organize devices in their corresponding bussesMartin Blumenstingl
The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2015-10-14ARM: meson6: DTS: Fix wrong reg mapping and IRQ numbersCarlo Caione
The DTS erronously uses the wrong reg mapping and IRQ numbers for some UART, WDT and timer nodes. Fix this. Reported-by: John Wehle <john@feith.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-03-02ARM: dts: meson: enable Ethernet controllerBeniamino Galvani
Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02ARM: dts: meson: add node for SPIFCBeniamino Galvani
This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Brown <broonie@kernel.org>
2014-12-11Merge tag 'media/v3.19-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - Two new dvb frontend drivers: mn88472 and mn88473 - A new driver for some PCIe DVBSky cards - A new remote controller driver: meson-ir - One LIRC staging driver got rewritten and promoted to mainstream: igorplugusb - A new tuner driver (m88rs6000t) - The old omap2 media driver got removed from staging. This driver uses an old DMA API and it is likely broken on recent kernels. Nobody cared enough to fix it - Media bus format moved to a separate header, as DRM will also use the definitions there - mem2mem_testdev were renamed to vim2m, in order to use the same naming convention taken by the other virtual test driver (vivid) - Added a new driver for coda SoC (coda-jpeg) - The cx88 driver got converted to use videobuf2 core - Make DMABUF export buffer to work with DMA Scatter/Gather and Vmalloc cores - Lots of other fixes, improvements and cleanups on the drivers. * tag 'media/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (384 commits) [media] mn88473: One function call less in mn88473_init() after error [media] mn88473: Remove uneeded check before release_firmware() [media] lirc_zilog: Deletion of unnecessary checks before vfree() [media] MAINTAINERS: Add myself as img-ir maintainer [media] img-ir: Don't set driver's module owner [media] img-ir: Depend on METAG or MIPS or COMPILE_TEST [media] img-ir/hw: Drop [un]register_decoder declarations [media] img-ir/hw: Fix potential deadlock stopping timer [media] img-ir/hw: Always read data to clear buffer [media] redrat3: ensure dma is setup properly [media] ddbridge: remove unneeded check before dvb_unregister_device() [media] si2157: One function call less in si2157_init() after error [media] tuners: remove uneeded checks before release_firmware() [media] arm: omap2: rx51-peripherals: fix build warning [media] stv090x: add an extra protetion against buffer overflow [media] stv090x: Remove an unreachable code [media] stv090x: Some whitespace cleanups [media] em28xx: checkpatch cleanup: whitespaces/new lines cleanups [media] si2168: add support for firmware files in new format [media] si2168: debug printout for firmware version ...
2014-11-26[media] ARM: dts: meson: add IR receiver nodeBeniamino Galvani
This adds a node for the IR remote control receiver to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2014-11-18ARM: dts: meson: add I2C controller nodesBeniamino Galvani
Add nodes for I2C controllers A,B,AO, which are available in both Meson6 and Meson8. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-18ARM: meson: DTS: enable L2 cacheBeniamino Galvani
This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-10-02ARM: DTS: meson: update DTSI to add watchdog nodeCarlo Caione
Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-09-25ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTSCarlo Caione
The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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