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2021-02-02ARM: dts: mmp2: Use symbolic names for audio clocksLubomir Rintel
These are slighly easier to read. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20210121034130.1381872-8-lkundrak@v3.sk' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add the GPULubomir Rintel
There's a GC860 2D + 3D core. Link: https://lore.kernel.org/r/20200718205019.184927-11-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add SSPA nodesLubomir Rintel
There are two I2S-capable audio serial port blocks. Link: https://lore.kernel.org/r/20200718205019.184927-9-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add Audio Clock controllerLubomir Rintel
This device generates the audio codec master clock and bit clock. Link: https://lore.kernel.org/r/20200718205019.184927-8-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add DMA nodesLubomir Rintel
There is a 16-channel peripheral DMA controller along with two-channel audio DMA engines. Link: https://lore.kernel.org/r/20200718205019.184927-7-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add Audio SRAMLubomir Rintel
This memory is region is where the two-channel audio DMA can pump sound samples into the SSPA's internal FIFO. Link: https://lore.kernel.org/r/20200718205019.184927-6-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Extend the MPMU reg rangeLubomir Rintel
The ACGR register is at the offset of 0x1024, beyond the 4k originally assigned to the MPMU range. Link: https://lore.kernel.org/r/20200718205019.184927-5-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22ARM: dts: mmp2: Add #power-domain-cells to /clocksLubomir Rintel
The power management unit, described by the soc_clocks node, controls the power to the peripherals by the means of power domains with a single cell -- the domain number. Link: https://lore.kernel.org/r/20200718205019.184927-4-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21ARM: dts: mmp*: Fix up encoding of the /rtc interrupts propertyLubomir Rintel
This way the device tree validator learns that each cell of the property constitutes a separate item. Otherwise it gets unnecessairly upset: mmp3-dell-ariel.dt.yaml: rtc@d4010000: interrupts: [[1, 0]] is too short Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-24ARM: dts: mmp*: Make the serial ports compatible with xscale-uartLubomir Rintel
XScale serial port driver is perfectly capable of supporting this hardware. A separate compatible string is probably a historical mess. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200320174107.29406-7-lkundrak@v3.sk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-24ARM: dts: mmp*: Fix serial port namesLubomir Rintel
A preferred node name for serial ports is "serial": mmp2-olpc-xo-1-75.dt.yaml: uart@d4030000: $nodename:0: 'uart@d4030000' does not match '^serial(@[0-9a-f,]+)*$' ... Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200320174107.29406-6-lkundrak@v3.sk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-07ARM: dts: mmp2: rename the USB PHY nodeLubomir Rintel
This device is not an OTG phy, it's a regular USB HS phy. Follow the generic node name recommendation, and rename it to "usb-phy". Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz>
2019-09-07ARM: dts: mmp2: specify reg-shift for the UARTsLubomir Rintel
This makes the 8250_of driver happy. There are two more drivers in the tree that bind to mrvl,mmp-uart compatibles: pxa and 8250_pxa and neither of them requires the reg-shift property, assuming it's always 2. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz>
2019-09-07ARM: dts: mmp2: add camera interfacesLubomir Rintel
Supported by the mmp-camera driver. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz>
2019-09-07ARM: dts: mmp2: fix the SPI nodesLubomir Rintel
The SPI bus has a single address cell and not size cells. Also, dtc thinks the SPI nodes are preferrably called "spi" and it is right to think so. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz>
2019-09-07ARM: dts: mmp2: trivial whitespace fixLubomir Rintel
A missing space before a curly brace. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 332Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as publishhed by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 48 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.292339952@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-11-30ARM: dts: mmp2: Add SSP controllersLubomir Rintel
Despite Marvel keeps their base addresses secret there's a good chance they're actually correct. SSP1 and SSP3 bases were taken from OLPC 1.75: OpenFirmware and kernel respectively. SSP2 and SSP4 addresses are from James Cameron who actually has a copy of the data sheet. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: add USB OTG host controllerLubomir Rintel
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: add OTG PHYLubomir Rintel
The USB OTG PHY chip. To be used by the OTG controller. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: add more TWSI controllersLubomir Rintel
I've gotten the base addresses, clocks and interrupts from an rusty and old out-of-tree driver. I haven't actually checked against the datasheet, since that one is reserved for the Marvell inner circle. Tested with an accelerometer on TWSI6 on an OLPC XO 1.75 machine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: fix TWSI2Lubomir Rintel
Marvell keeps their MMP2 datasheet secret, but there are good clues that TWSI2 is not on 0xd4025000 on that platform, not does it use IRQ 58. In fact, the IRQ 58 on MMP2 seems to be a signal processor: arch/arm/mach-mmp/irqs.h:#define IRQ_MMP2_MSP 58 I'm taking a somewhat educated guess that is probably a copy & paste error from PXA168 or PXA910 and that the real controller in fact hides at address 0xd4031000 and uses an interrupt line multiplexed via IRQ 17. I'm also copying some properties from TWSI1 that were missing or incorrect. Tested on a OLPC XO 1.75 machine, where the RTC is on TWSI2. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: add MMC controllersLubomir Rintel
There's apparently four of them on a MMP2. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: add clock to the timerLubomir Rintel
The timer needs the timer clock to be enabled, otherwise it stops ticking. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: give gpio node a nameLubomir Rintel
This will be useful for boards that actually use GPIO pins. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-11-30ARM: dts: mmp2: fix the gpio interrupt cell numberLubomir Rintel
gpio-pxa uses two cell to encode the interrupt source: the pin number and the trigger type. Adjust the device node accordingly. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-11-12arm: mmp: Make use of the DT supported clockChao Xie
Change the dtsi and dts file, soc initialization code to make use of DT support clock. So now in the code we do only need call of_clk_init to initialize the clocks. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12arm: mmp: Make all the dts file to be compiled by MakefileChao Xie
Add items in arch/arm/boot/dt/Makefile to compile the dtb for mach-mmp. Change the dts and dtsi file to use #include instead of \include\ Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2013-04-11ARM: mmp: add more compatible names in gpio driverHaojian Zhuang
Since more driver names are added into platform id, do the same thing on compatible names for DT mode. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-14mfd: max8925: Add dtsQing Xu
Add max8925 dts support into mmp2 brownstone platform Signed-off-by: Qing Xu <qingx@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2012-08-16ARM: mmp: enable tauros2 cache in mmp2 dtHaojian Zhuang
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-05-05ARM: dts: refresh dts file for arch mmpHaojian Zhuang
Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq, timer, gpio components. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>