summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/r8a77470.dtsi
AgeCommit message (Collapse)Author
2022-09-19ARM: dts: renesas: Fix USB PHY device and child node namesGeert Uytterhoeven
make dtbs_check: usb-phy@e6590100: '#phy-cells' is a required property From schema: dtschema/schemas/phy/phy-provider.yaml The R-Car Gen2 USB PHY device nodes do not represent USB PHYs theirselves, and thus do not have "#phy-cells" properties. Fix the warning by renaming them from "usb-phy" to "usb-phy-controller". Rename their child nodes from "usb-channel" to "usb-phy", as these do represent USB PHYs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/6442b4042e26537abc8632c4772f8201685f1f1f.1663165098.git.geert+renesas@glider.be
2022-04-13ARM: dts: rzg1: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-25ARM: dts: renesas: Move enable-method to CPU nodesGeert Uytterhoeven
According to Documentation/devicetree/bindings/arm/cpus.yaml, the "enable-method" property should be a property of the individual CPU nodes, and not of the parent "cpus" container node. However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the "cpus" node instead. Secondary CPU bringup and CPU hot (un)plug work regardless, as arm_dt_init_cpu_maps() falls back to looking in the "cpus" node. The cpuidle code does not have such a fallback, so it does not detect the enable-method. Note that cpuidle does not support the "renesas,apmu" enable-method yet, so for now this does not make any difference. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
2021-05-25ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names listAdam Ford
The bindings have been updated to support two clocks. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210224115146.9131-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-08ARM: dts: renesas: Group tuples in APMU cpus propertiesGeert Uytterhoeven
To improve human readability and enable automatic validation, the tuples in "cpus" properties in device nodes for Advanced Power Management Units for AP-System Core (APMU) should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210204130517.1647073-2-geert+renesas@glider.be
2020-09-11ARM: dts: renesas: Fix pin controller node namesGeert Uytterhoeven
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be
2020-07-17ARM: dts: renesas: Fix SD Card/eMMC interface device node namesYoshihiro Shimoda
Fix the device node names as "mmc@". Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") Fixes: a49f76cddaee ("ARM: dts: r7s9210: Add SDHI support") Fixes: 43304a5f5106 ("ARM: shmobile: r8a73a4: tidyup DT node naming") Fixes: 7d907894bfe3 ("ARM: shmobile: r8a7740: tidyup DT node naming") Fixes: 3ab2ea5fd1ce ("ARM: dts: r8a7742: Add SDHI nodes") Fixes: 63ce8a617b51 ("ARM: dts: r8a7743: Add SDHI controllers") Fixes: b591e323b271 ("ARM: dts: r8a7744: Add SDHI nodes") Fixes: d83010f87ab3 ("ARM: dts: r8a7744: Initial SoC device tree") Fixes: 7079131ef9b9 ("ARM: dts: r8a7745: Add SDHI controllers") Fixes: 0485da788028 ("ARM: dts: r8a77470: Add SDHI1 support") Fixes: 15aa5a95e820 ("ARM: dts: r8a77470: Add SDHI0 support") Fixes: f068cc816015 ("ARM: dts: r8a77470: Add SDHI2 support") Fixes: 14e1d9147d96 ("ARM: shmobile: r8a7778: tidyup DT node naming") Fixes: 2624705ceb7b ("ARM: shmobile: r8a7779: tidyup DT node naming") Fixes: b718aa448378 ("ARM: shmobile: r8a7790: tidyup DT node naming") Fixes: b7ed8a0dd4f1 ("ARM: shmobile: Add SDHI devices to r8a7791 DTSI") Fixes: ce01b14ecf19 ("ARM: dts: r8a7792: add SDHI support") Fixes: fc9ee228f500 ("ARM: dts: r8a7793: Add SDHI controllers") Fixes: b8e8ea127d00 ("ARM: shmobile: r8a7794: add SDHI DT support") Fixes: 33f6be3bf6b7 ("ARM: shmobile: sh73a0: tidyup DT node naming") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1594382936-14114-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-02-24ARM: dts: rzg1: Add reset control properties for displayGeert Uytterhoeven
Add reset control properties to the devices node for the Display Units on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a single reset for all DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200218133019.22299-3-geert+renesas@glider.be
2019-12-31ARM: dts: rcar-gen2: Add missing mmio-sram bus propertiesGeert Uytterhoeven
"#address-cells", "#size-cells", and "ranges" are required properties for devices nodes compatible with "mmio-sram", leading to warnings when running "make dtbs_check": $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sram/sram.yaml arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#address-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#size-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: 'ranges' is a required property ... Fix this by adding the missing properties to the mmio-sram device nodes in the DTS files for all affected R-Car Gen2 and RZ/G1 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213162604.1890-1-geert+renesas@glider.be
2019-12-20ARM: dts: renesas: Group tuples in interrupt propertiesGeert Uytterhoeven
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. While "make dtbs_check" does not impose this yet for the "interrupts" property, it does for the "interrupt-map" property, leading to warnings like: pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long Fix this by grouping the tuples of the "interrupts" and "interrupt-map" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-08-21ARM: dts: r8a77470: Add PMU device nodeGeert Uytterhoeven
Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on RZ/G1C by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
2019-04-12ARM: dts: r8a77470: Add HSUSB device nodesBiju Das
Define the r8a77470 generic part of the HSUSB0/1 device nodes. Currently the renesas_usbhs driver doesn't handle multiple phys and we don't have a proper hardware to validate such driver changes. So for hsusb1 it is assumed that usbphy0 will be enabled by either channel0 host or device. In future, if any boards support hsusb1, we will need to add multiple phy support in the renesas_usbhs driver and override the board dts to enable the same. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) deviceBiju Das
Define the r8a77470 generic part of the USB2.0 Host Controller device nodes (ehci[01]/ohci[01]). Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB PHY DT supportBiju Das
Define the r8a77470 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add VIN supportCao Van Dong
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add PWM supportCao Van Dong
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add HSCIF supportCao Van Dong
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-25ARM: dts: r8a77470: Add DU supportFabrizio Castro
This commit adds DU support to the RZ/G1C (a.k.a. r8a77470) specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add QSPI supportFabrizio Castro
Add QSPI[01] support to the RZ/G1C SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add CMT SoC specific supportBiju Das
Add CMT[01] support to r8a77470 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add USB-DMAC device nodesBiju Das
This patch adds USB DMAC nodes. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add watchdog support to SoC dtsiBiju Das
This patch adds watchdog support to the r8a77470 SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> [simon: moved node to preserve sort order] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add SDHI1 supportFabrizio Castro
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a. r8a77470) is compatible with the R-Car Gen3 ones, its OF compatibility is restricted to the SoC specific compatible string to avoid confusion, as from a more generic perspective the RZ/G1C is sharing the most similarities with the R-Car Gen2 family of SoCs, and there is a combination of R-Car Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP on this specific chip. This patch adds the SoC specific part of SDHI1 support, and since SDHI1 comes with internal DMA, its DT node looks fairly different from SDHI0 and SDHI2. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add SDHI0 supportFabrizio Castro
RZ/G1C comes with two different types of IP for the SDHI interfaces, SDHI0 and SDHI2 share the same IP type, and such an IP is also compatible with the one found in R-Car Gen2. SDHI1 IP on the other hand is compatible with R-Car Gen3 with internal DMA. This patch completes the SDHI support of the R-Car Gen2 compatible IPs, including fixing the max-frequency definition of SDHI2, as it turns out there is a bug in Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev. 1.00 Oct. 2017). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add I2C[0123] supportFabrizio Castro
Add device tree nodes for the I2C[0123] controllers. Also, add the aliases node. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28ARM: dts: r8a77470: Add I2C4 supportFabrizio Castro
Add I2C4 support to RZ/G1C (a.k.a. r8a77470) SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28ARM: dts: r8a77470: Add SDHI2 supportFabrizio Castro
Add SoC specific device tree definitions for the SDHI2 interface. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28ARM: dts: r8a77470: Add SMP supportFabrizio Castro
Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27ARM: dts: r8a77470: Add GPIO supportBiju Das
Describe GPIO blocks in the R8A77470 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27ARM: dts: r8a77470: Add PFC supportBiju Das
Define the generic R8A77470 part of the PFC device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27ARM: dts: r8a77470: Use r8a77470-sysc binding definitionsBiju Das
Replace the hardcoded power domain indices by R8A77470_PD_* symbols. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23ARM: dts: r8a77470: Use r8a77470-cpg-mssr binding definitionsGeert Uytterhoeven
Replace the hardcoded clock indices by R8A77470_CLK_* symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-30ARM: dts: r8a77470: Add EtherAVB supportBiju Das
Define the generic R8A77470 part of the EtherAVB device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a77470: Add SCIF DMA supportBiju Das
Add SCIF DMA support for R8A77470 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a77470: Add SCIF supportBiju Das
Describe SCIF ports in the R8A77470 device tree. Also it fixes the CPG clock index ZS from 6 to 5. Fixes: 6929dfc5918049 ("ARM: dts: r8a77470: Initial SoC device tree") Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a77470: Add IRQC supportBiju Das
Describe the IRQC interrupt controller in the R8A77470 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a77470: Add SYS-DMAC supportBiju Das
Describe SYS-DMAC0/1 in the R8A77470 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-16ARM: dts: r8a77470: Initial SoC device treeBiju Das
The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit (git 2.34.1) at 2024-06-21 09:37:02 +0000