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2019-06-27ARM: dts: rockchip: add display nodes for rk322xJustin Swartz
Add display_subsystem, hdmi_phy, vop, and hdmi device nodes plus a few hdmi pinctrl entries to allow for HDMI output. Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> [added assigned-clock settings for hdmiphy output] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27ARM: dts: rockchip: fix vop iommu-cells on rk322xJustin Swartz
iommu-cells obviously needs to start with a "#". Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: rockchip: bulk convert gpios to their constant counterpartsHeiko Stuebner
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-19ARM: dts: rockchip: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-06-17ARM: dts: rockchip: Add missing cooling device properties for CPUs on rk322xViresh Kumar
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-06-17ARM: dts: rockchip: use SPDX-License-IdentifierKlaus Goger
Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-04-16ARM: dts: rockchip: add clocks in iommu nodesJeffy Chen
Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-28Merge tag 'v4.17-rockchip-dts32-1' of ↵Arnd Bergmann
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "Rockchip dts32 changes for 4.17" from Heiko Stübner: For general soc-specific changes the rk322x socs got their correct grf compatible set. Other than that there are some board-specific changes like the Rock2 getting its otg port, recovery and power keys enabled. The vyasa board gained an enabled emmc node and the phyCORE boards got UHS speeds in their sd card and a fixed sd-card power supply. Finally the veyron boards dropped a nonstandard and unused property. * tag 'v4.17-rockchip-dts32-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: enable USB-OTG port on Radxa Rock2 Square ARM: dts: rockchip: add recovery button for Rock2 Square ARM: dts: rockchip: add power key for Rock2 Square ARM: dts: rockchip: Add eMMC node for rk3288-vyasa ARM: dts: rockchip: Support UHS mode for SD card on phyCORE-RK3288 RDK ARM: dts: rockchip: Fix supply node for card's power on phycore som ARM: dts: rockchip: add "rockchip,rk3228-grf" compatible for rk322x grf node ARM: dts: rockchip: drop veyron's nonstandard 'backlight-boot-off'
2018-02-16ARM: dts: rockchip: Fix DWMMC clocksRobin Murphy
Trying to boot an RK3328 box with an HS200-capable eMMC, I see said eMMC fail to initialise as it can't run its tuning procedure, because the sample clock is missing. Upon closer inspection, whilst the clock is present in the DT, its name is subtly incorrect per the binding, so __of_clk_get_by_name() never finds it. By inspection, the drive clock suffers from a similar problem, so has never worked properly either. This error has propagated across the 32-bit DTs too, so fix those up. Fixes: 187d7967a5ee ("ARM: dts: rockchip: add the sdio/sdmmc node for rk3036") Fixes: faea098e1808 ("ARM: dts: rockchip: add core rk3036 dtsi") Fixes: 9848ebeb952d ("ARM: dts: rockchip: add core rk3228 dtsi") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-02-12ARM: dts: rockchip: add "rockchip,rk3228-grf" compatible for rk322x grf nodeShawn Lin
rockchip,rk3228-grf is used both for rk3228 and rk3229. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-10-10ARM: dts: rockchip: fix mali400 ppmmu interrupt namesHeiko Stuebner
The interrupts were wrongly named as ppXmmu while the binding specifies them as ppmmuX. Fix that for the recently added Utgard mali nodes on Rockchip socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-22ARM: dts: rockchip: add rk322x gpu nodeHeiko Stuebner
The rk3228/3229 uses a Mali400 GPU with two pixel processors. This adds the core node for it, which can be enabled in board devicetrees. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-21ARM: dts: rockchip: add rk322x iommu nodesSimon Xue
Add VPU/VDEC/VOP/IEP iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-06ARM: dts: rockchip: add spi node and spi pinctrl on rk3228/rk3229Huibin Hong
Add spi node and spi pinctrl for rk322x Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-17ARM: dts: rockchip: add efuse device node for rk3228Finley Xiao
Add a efuse node in the device tree for the rk3228 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoCShawn Lin
This patch adds sdmmc/sdio controller nodes for rk3228 SoC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoCShawn Lin
This adds amend compatible content for eMMC of RK3228 SoC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: add cpu enable method for rk3228 SoCFrank Wang
This patch sets PSCI as the default cpu enable-method for RK3228 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: remove num-slots from all platformsShawn Lin
We deprecated the "num-slots" property now and plan to get rid of it finally. Just move a step to cleanup it from DT. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: Add io-domain node for rk3228David Wu
This patch adds io-domain support for rk3228 SoC. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: add rk322x spdif nodeSugar Zhang
This patch add spdif node for rk322x. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02ARM: dts: rockchip: add usb nodes on rk322xWilliam Wu
This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-19ARM: dts: rockchip: set a sane frequence for tsadc on rk322xRocky Hao
Update freq of tsadc's working clock as 32768 hz, if not set, tsadc will work at a default frequence. Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-19ARM: dts: rockchip: add operating-points-v2 for cpu on rk322xFinley Xiao
This patch adds a new opp table for cpu on rk322x SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-19ARM: dts: rockchip: set default rates for core clocks on rk322xElaine Zhang
Set sane default frequencies for CPLL, GPLL and some other core clocks on the rk322x. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17ARM: dts: rockchip: add second uart2 pinctrl on rk322xFrank Wang
Add secondary pinctrl set for UART2 which can be used to prevent conflicts with sdmmc pins. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17ARM: dts: rockchip: correct rk322x uart2 pinctrlFrank Wang
Correct UART2 PINCTRL flag to use the correct pull up setting Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17ARM: dts: rockchip: add watchdog device node on rk322xFrank Wang
Add watchdog device node for rk322x SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17ARM: dts: rockchip: fix rk322x i2s1 pinctrl errorSugar Zhang
Refer to Chapter 5.3.2 of rk3229 TRM, we can see that GPIO1A[2,4,5] using RK_FUNC_2 not RK_FUNC_1. This patch fixes it. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-09Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM Device-tree updates from Olof Johansson: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. Major new platforms: - Gemini has been ported to DT, so a handful of "new" platforms moved over from board files - Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK - A bunch of embedded platforms, several Linksys platforms, Synology DS116, - Motorola Droid4 (really old OMAP-based phone) support is added. Some refactorings, i.e. Allwinner H3/H5 support is commonalized. And lots of smaller changes, cleanups, etc. See shortlog for more description We're adding ability to cross-include DT files between arm and arm64, by creating appropriate links in the dt-include directory, and using arm/ and arm64/ as include prefixes. This will avoid other local hacks such as per-file links between the two arch trees (this broke for external mirroring of DT contents). Now they can just provide their own appropriate dt-include hierarcy per platform" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits) ARM: dts: exynos: Use - instead of @ for DT OPP entries arm: spear6xx: add DT description of the ADC on SPEAr600 arm: spear6xx: remove unneeded pinctrl properties in spear600-evb arm: spear6xx: switch spear600-evb to the new flash partition DT binding arm: spear6xx: fix spaces in spear600-evb.dts arm: spear6xx: use node labels in spear600-evb.dts arm: spear6xx: add labels to various nodes in spear600.dtsi ARM: dts: vexpress: fix few unit address format warnings ARM: dts: at91: sama5d3_xplained: not all ADC channels are available ARM: dts: at91: sama5d3_xplained: fix ADC vref ARM: dts: at91: add envelope detector mux to the Axentia TSE-850 ARM: dts: armada-38x: label USB and SATA nodes ARM: dts: imx6q-utilite-pro: add hpd gpio ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply ARM: dts: imx6qdl-sabresd: Set LDO regulator supply ARM: dts: imx: add Gateworks Ventana GW5903 support ARM: dts: i.MX25: add AIPS control registers ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators ARM: dts: imx7-colibri: remove 1.8V fixed regulator ARM: dts: imx7-colibri: allow to disable Ethernet rail ...
2017-04-07ARM: dts: rockchip: Update compatible property for rk322x timerAlexander Kochetkov
Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"' to match devicetree bindings. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Suggested-by: Heiko Stübner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2017-03-16ARM: dts: rockchip: add rk322x dw-mmc resetsHeiko Stuebner
dw-mmc got its reset-properties specified, so add the softresets for it in rk3228/rk3229. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-02-07ARM: DTS: Fix register map for virt-capable GICMarc Zyngier
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-09ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"Jaehoon Chung
In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsiJavier Martinez Canillas
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27ARM: dts: rockchip: add GMAC nodes for RK322x SoCsXing Zheng
This patch add the GMAC dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27ARM: dts: rockchip: add i2s nodes for RK322x SoCsXing Zheng
This patch add the i2s dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsiXing Zheng
We have the brother chipset that RK3228 and RK3229, they share most of dts configuration, but there are a number of different features. In order to develop the future when they are easy to distinguish, we need them to be independent. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2024-06-03 16:49:31 +0000