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Fix the whole mux-mask table according to datasheet for the sam9x60
product. Too much functions for pins were disabled leading to
misunderstandings when enabling more peripherals or taking this table
as an example for another board.
Take advantage of this fix to move the mux-mask in the SoC file where it
belongs and use lower case letters for hex numbers like everywhere in
the file.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Cc: <stable@vger.kernel.org> # 5.6+
Cc: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210310152006.15018-1-nicolas.ferre@microchip.com
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Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.
Besides smaller fixes, some refactorings and cleanups, some of the new
platforms and chips (or significant features) supported are below:
Broadcom boards:
- Cisco Meraki MR32 (BCM53016-based)
- BCM2711 (RPi4) display pipeline support
Actions Semi boards:
- Caninos Loucos Labrador SBC (S500-based)
- RoseapplePi SBC (S500-based)
Allwinner SoCs/boards:
- A100 SoC with Perf1 board
- Mali, DMA, Cetrus and IR support for R40 SoC
Amlogic boards:
- Libretch S905x CC V2 board
- Hardkernel ODROID-N2+ board
Aspeed boards/platforms:
- Wistron Mowgli (AST2500-based, Power9 OpenPower server)
- Facebook Wedge400 (AST2500-based, ToR switch)
Hisilicon SoC:
- SD5203 SoC
Nvidia boards:
- Tegra234 VDK, for pre-silicon Orin SoC
NXP i.MX boards:
- Librem 5 phone
- i.MX8MM DDR4 EVK
- Variscite VAR-SOM-MX8MN SoM
- Symphony board
- Tolino Shine 2 HD
- TQMa6 SoM
- Y Soft IOTA Orion
Rockchip boards:
- NanoPi R2S board
- A95X-Z2 board
- more Rock-Pi4 variants
STM32 boards:
- Odyssey SOM board (STM32MP157CAC-based)
- DH DRC02 board
Toshiba SoCs/boards:
- Visconti SoC and TPMV7708 board"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
ARM: dts: nspire: Fix SP804 users
arm64: dts: lg: Fix SP804 users
arm64: dts: lg: Fix SP805 clocks
ARM: mstar: Fix up the fallout from moving the dts/dtsi files
ARM: mstar: Add mstar prefix to all of the dtsi/dts files
ARM: mstar: Add interrupt to pm_uart
ARM: mstar: Add interrupt controller to base dtsi
ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
arm64: dts: ti: k3-j7200-main: Add USB controller
arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
ARM: dts: hisilicon: add SD5203 dts
ARM: dts: hisilicon: fix the system controller compatible nodes
arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
arm64: dts: zynqmp: Remove undocumented u-boot properties
arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
...
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Enable usb device for sam9x60ek board.
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
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The memory node requires a unit-address, add it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20200831171129.3886857-7-alexandre.belloni@bootlin.com
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The ranges, #address-cells and #size-cells properties are mandatory, add
them to the sram nodes.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20200831171129.3886857-4-alexandre.belloni@bootlin.com
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The reg property is mandatory for cpu nodes, also fix the #address-cells of
the cpus node that has to be at least 1.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20200831171129.3886857-2-alexandre.belloni@bootlin.com
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Add RTT. Allong with it enable GBPR as it is requested by RTT.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1591779936-18577-4-git-send-email-claudiu.beznea@microchip.com
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Add node for watchdog timer.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lore.kernel.org/r/1581408369-14469-1-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/1579085987-13976-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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