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2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add reset properties for DMADinh Nguyen
Add both the reset and reset-ocp properties for the DMA node on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add the QSPI OCP reset property on arria10Dinh Nguyen
The QSPI module needs the OCP reset bit deasserted as well. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-06-10ARM: dts: arria10: Add EMAC OCP reset propertyDinh Nguyen
Add the EMAC's OCP reset property on Arria10. The OCP reset bits are also needed to correctly bring the EMACs out of reset correctly. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-06-06ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" bindingDinh Nguyen
Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Arria10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Arria10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-14ARM: dts: socfpga: update missing reset property peripheralsDinh Nguyen
Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga: remove dma-mask propertyDinh Nguyen
The dma-mask property has been removed from the NAND driver. Remove the property from the DTS files. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-27ARM: dts: socfpga: Fix SDRAM node address for Arria10Thor Thayer
The address in the SDRAM node was incorrect. Fix this to agree with the correct address and to match the reg definition block. Cc: stable@vger.kernel.org Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30ARM: dts: arria10: update NAND clockingDinh Nguyen
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). This patch adds a nand_clk, which is derived from the nand_x_clk, but has a fixed divider of 4, and the nand_ecc_clk, which is derived from the nand_x_clk. Update the NAND node to use the additional clocks. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: add nand_ecc_clk and update commit message
2018-08-30ARM: dts: socfpga: set timer interrupt to edge sensitiveSilvan Murer
Change timer interrupt to edge sensitive. Signed-off-by: Silvan Murer <silvan.murer@gmail.com> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-07-02ARM: dts: Add SPI0 node for Arria10Thor Thayer
Add the SPI0 node for Arria10. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-06-26ARM: dts: Fix SPI node for Arria10Thor Thayer
Remove the unused bus-num node and change num-chipselect to num-cs to match SPI bindings. Cc: stable@vger.kernel.org Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatible for Arria10Dinh Nguyen
The NAND compatible "denali,denal-nand-dt" property has never been used and is obsolete. Remove it. Cc: stable@vger.kernel.org Fixes: f549af06e9b6("ARM: dts: socfpga: Add NAND device tree for Arria10") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA device trees already contain the nodes that are defined in skeleton.dtsi (#address-cells, #size-cells, chosen, aliases, memory). Including skeleton.dtsi is useless and will produce the following warning when compiled with W=1: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard
Node eccmgr has a unit name, but do not have a reg property as only the child nodes do have this property. Likewise the usbphy node do not have a reg property. This will trigger the following warnings when compiled with W=1: Node /soc/eccmgr@ffd08140 has a unit name, but no reg property Node /soc/usbphy@0 has a unit name, but no reg property Remove the superfluous unit names. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but does not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-02-02ARM: dts: Add EMAC AXI settings for Arria10Thor Thayer
Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen
Add "altr,sdr-ctl" to the SDRAM controller node. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add fpga region support on Arria10Dinh Nguyen
Add the base FPGA region for DT overlay support in FPGA programming. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-05ARM: dts: socfpga: Add NAND device tree for Arria10Graham Moore
Add socfpga_arria10_socdk_nand.dts board file for supporting NAND. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: move nand dts node to socfpga_arria10.dtsi
2017-01-04ARM: dts: socfpga: add fpga-manager node for Arria10Dinh Nguyen
Add the FPGA manger DTS entry for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-08ARM: dts: socfpga: Add QSPI node for the Arria10Dinh Nguyen
Add the QSPI device node for Arria10 SOC. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chipThor Thayer
Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-08-08ARM: dts: Add Arria10 USB EDAC devicetree entryThor Thayer
Add the device tree entries needed to support the Altera USB FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1468512408-5156-11-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-08ARM: dts: Add Arria10 DMA EDAC devicetree entryThor Thayer
Add the device tree entries needed to support the Altera DMA FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1468512408-5156-10-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-01Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
2016-06-27ARM: dts: Add Arria10 Ethernet EDAC devicetree entryThor Thayer
Add the device tree entries needed to support the Altera Ethernet FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1466603939-7526-9-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-06-08ARM: dts: socfpga: fix definitions of serial consoleMatthew Gerlach
The notion of which uart instance is serial0 or serial1 is board specific rather than generic to the chip. This patch removes the serial aliases from generic chip dtsi and adds an appropriate alias to the board specific dtsi. By making the alias for serial0 point to uart1 for the arria10_socdk, the linux boot command line supports specifying console=ttyS0,115200 for backwards compatibility, and it supports not specifying the console at all. Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03ARM: dts: Move Arria10 SDRAM as child of ECC ManagerThor Thayer
Changes to support ECC Manager as SDRAM IRQ parent by 1) updating IRQ property values to correct child IRQs 2) moving node under ECC Manager. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03ARM: dts: Arria10 ECC Manager IRQ controller changesThor Thayer
Changes to support IRQ controller implementation including adding new property irq-controller to eccmgr and adding IRQ property to children. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen
Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entryThor Thayer
Add the device tree entries needed to support the Altera On-Chip RAM EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entryThor Thayer
Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMAGraham Moore
The PL330 DMA driver will not load on Arria10 without devicetree entries for clocks and clock_names. This patch adds those entries. It also adds the ninth interrupt, which is required for error detection. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add the clk-phase property for sd/mmc clockDinh Nguyen
The CIU clock for the SD/MMC should be the sdmmc_clk and not the sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-03-12ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada
The compatible string "simple-bus" is well defined in ePAPR, while I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or Documentation/devicetree/. DT is also used by other projects than Linux kernel. It is not a good idea to rely on such an unofficial binding. This commit - replaces "arm,amba-bus" with "simple-bus" - drops "arm,amba-bus" where it is used along with "simple-bus" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-06ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10Dinh Nguyen
Add the required clock fields for all the I2C nodes. Also add missing clock fields for UART0 and USB1. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.3, take 2 - Add DTS property "altr,modrst-offset" for reset driver to use - Add updated reset defines for the reset driver - Add reset property for EMACs on Arria10 * tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: Add resets for EMACs on Arria10 ARM: socfpga: dts: add "altr,modrst-offset" property dt-bindings: Add reset manager offsets for Arria10 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-09ARM: socfpga: dts: Add resets for EMACs on Arria10Dinh Nguyen
Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen
The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20ARM: dts: socfpga: use stdout-path for chosen nodeDinh Nguyen
Use stdout-path dts property for kernel console. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-26Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Kevin Hilman: "As usual, quite a few device-tree updates in ARM land. There was one minor churn in DTs due to relicensing under a dual-license, and lots of little additions of new peripherals, features etc, but nothing really exciting to call to your attention. Some higlights, focsuing on support for new SoCs and boards: - AT91: new boards: Overkiz, Acme Systems' Arietta G25 - tegra: HDA support - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys boards, DLink DNS-327L - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50 - ARM: added support for Juno r1 board - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6, Gateworks GW5510, and aristainetos2 boards - hisilicon: hi6220 SoC support; new boards: 96boards hikey" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits) ARM: hisi: revert changes from hisi/hip04-dt branch ARM: nomadik: set proper compatible for accelerometer ARM64: juno: add GPIO keys ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes ARM: dts: Introduce STM32F429 MCU ARM: socfpga: dts: enable ethernet for Arria10 devkit ARM: dts: k2l: fix the netcp range size ARM: dts: k2e: fix the netcp range size ARM: dts: k2hk: fix the netcp range size ARM: dts: k2l-evm: Add device bindings for netcp driver ARM: dts: k2e-evm: Add device bindings for netcp driver ARM: dts: k2hk-evm: Add device bindings for netcp driver ARM: BCM5301X: Add DT for Asus RT-AC87U ARM: BCM5301X: add IRQ numbers for PCIe controller ARM: BCM5301X: add NAND flash chip description arm64: dts: Add dts files for Hisilicon Hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC ARM: at91/dt: sama5d4ek: mci0 uses slot 0 ARM: at91/dt: kizbox: fix mismatch LED PWM device ...
2015-06-24arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS supportThor Thayer
Add support for the Arria10 SDRAM EDAC. Update the bindings document for the new match string. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2015-06-10ARM: socfpga: dts: enable ethernet for Arria10 devkitDinh Nguyen
Update the arria10 gmac nodes with all the necessary properties for ethernet to function on the Arria10 devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10Merge tag 'socfpga_dts_for_v4.2_part_3' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA updates for v4.2 part 3 - Add SCU node for Arria 10 - Add enable-method for cpu nodes - Add SDRAM controller binding doc - Enable gpio-leds on SoCFPGA Socrates board * tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: socrates: add gpio-leds ARM: socfpga: socrates: enable gpio0/1 ARM: socfpga: dts: add sdram controller dt binding doc ARM: socfpga: dts: add enable-method property for cpu nodes ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-02ARM: socfpga: dts: add enable-method property for cpu nodesDinh Nguyen
Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02ARM: socfpga: dts: add the a9-scu node for arria10Dinh Nguyen
Add a dts node for the A9 SCU on the Arria10 platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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