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path: root/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
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2017-03-06ARM: dts: socfpga: Add unit name to memory nodesFlorian Vaussard
Memory nodes in Arria5, Cyclone5 and Arria10 do not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /memory has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-08ARM: dts: socfpga: add specific compatible strings for boardsDinh Nguyen
Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: Be a bit more specific with the c5 dk and sockit, use "altr,socfpga-cyclone5-socdk" and "terasic,socfpga-cyclone5-sockit" v2: remove extra space and add a comma between compatible entries
2016-06-08ARM: dts: socfpga: Add missing PHY phandleMarek Vasut
Add missing PHY phandle into the DT, otherwise the stmmac code won't detect the PHY correctly anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-22ARM: dts: socfpga: Add samtec VIN|ING boardMarek Vasut
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>