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path: root/arch/arm/boot/dts/stih407-pinctrl.dtsi
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2015-10-15ARM: dts: Fix RGMII pinctrl timingsMaxime Coquelin
These new re-timing values provides a better stability on Ethernet link. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Rename incorrect interrupt related bindingLee Jones
interrupts-names => interrupt-names Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add RMII pinctrl supportPeter Griffin
This patch adds the RMII pinctrl support for the Synopsys MAC on STiH407 SoCs. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TXPeter Griffin
This patch adds the pinconfig for IRB TX and IRB UHF. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SD pinctrl config for mmc0 controllerPeter Griffin
This patch adds the missing SD pinctrl config for mmc/sd controller 0. This is required to enable the B2144A daughter board that exposes this controller as a sd slot. Signed-off-by: Nebil BEN MEFTEH <nebil.ben-mefteh@st.com> Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add systrace pin configurationPeter Griffin
This patch adds the pin config for systrace for STiH407 family silicon. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add NAND flash controller pin configurationPeter Griffin
This patch adds NAND flash support controller pin configuration for STiH407 family silicon. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin configPeter Griffin
This patch adds the pin configuration for the NOR flash controller. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add serial3 pinctrl configurationPeter Griffin
Add missing serial 3 pinctrl config. This can be used on b2206 HVK, where it defaults to PIO31[3] & PIO31[4], alternate 1. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Carmelo Amoroso <carmelo.amoroso@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configsPeter Griffin
This patch adds the spi pinctrl configurations for all SPI controllers, and also the alternate muxings which can be used depending on board design. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Add i2c3 alternate pin configsPeter Griffin
i2c3 controller can use several sets of pins depending on board design. This patch adds the missing alternate pinconfigs. Signed-off-by: Seraphin Bonnaffe <seraphin.bonnaffe@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Add a cec0 pin definitionPeter Griffin
This pin setup provides the correct configuration in order to interact with the CEC HW. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Nicolas Vanhaelewyn <nicolas.vanhaelewyn@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configurationPeter Griffin
mtsin0 channel can only be configured for parallel data transfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsout1 pinctrl configurationPeter Griffin
tsout1 channel can only be configured for serial data tranfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsout0 pinctrl configurationPeter Griffin
tsout0 channel can be configured for either serial or parallel data transfer. Both pin configurations are provided. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin5 pinctrl configurationPeter Griffin
tsin5 can only be configured for serial data transfer. However depending on board design, two alternate tsin5 pin configurations are available, both in pin-controller-front0. pinctrl_tsin5_serial_alt1 is brought out on B2120 reference design as TSD on NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin4 pinctrl configurationPeter Griffin
tsin4 can only be configured for serial data transfer. However depending on board design, two alternate pin configurations are available. One in pin-controller-front0 and the other in pin-controller-front1. pinctrl_tsin4_serial_alt3 is brought out on B2120 reference design as TSC on NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin3 pinctrl configurationPeter Griffin
tsin3 channel can only be configured for serial data transfer. On B2120 reference design tsin3 is brought out as TSB on the NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin2 pinctrl configurationPeter Griffin
tsin2 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin1 pinctrl configurationPeter Griffin
tsin1 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin0 pinctrl configurationPeter Griffin
tsin0 and be configured as either serial or parallel. This patch adds the pinctrl config for both possiblities. On B2120 reference design tsin0 is brought out as TSA on the NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-04-30ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35Karim BEN BELGACEM
This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM <karim.ben-belgacem@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21ARM: dts: Add STiH407 SoC supportMaxime Coquelin
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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