| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-08-23 | ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 | Icenowy Zheng | |
| Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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