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No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Enable Tegra based keyboard controller and populate the key mapping
for Whistler.
With this patch, HOME, BACK, POWER and MENU keys will work.
Still other keys which are in ROW3 and ROW4 will not work as it
conflicts with KBC pins on SDIO2 pinmux.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use engineering name 'Tegra20' instead of 'Tegra2'
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD,
and a VGA output. tegradrm doesn't support either of those output types
yet.
Based on work by Thierry Reding for TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Commit 13511de "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
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Add DT property to tell the MAX8907 that it should provide the
pm_power_off() implementation. This allows "shutdown" to work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Whistler uses a Maxim 8907 regulator. Instantiate this.
The voltage settings were derived from the schematic. The only exception
is the BBAT voltage; the schematic says 1.2v, but the HW can't go that
low, so use the HW default of 2.4v instead.
Almost all regulators list all driven supply signal names in their
regulator-names property. The exception is nvvdd_sv3, which is in turn
named 12 more different names on the schematic, so these were omitted
for brevity.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:
E1120 motherboard
E1108 CPU board
E1116 PMU board
The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.
Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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