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path: root/arch/arm/mach-imx/suspend-imx6.S
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2020-02-13ARM: imx: build v7_cpu_resume() unconditionallyAhmad Fatoum
This function is not only needed by the platform suspend code, but is also reused as the CPU resume function when the ARM cores can be powered down completely in deep idle, which is the case on i.MX6SX and i.MX6UL(L). Providing the static inline stub whenever CONFIG_SUSPEND is disabled means that those platforms will hang on resume from cpuidle if suspend is disabled. So there are two problems: - The static inline stub masks the linker error - The function is not available where needed Fix both by just building the function unconditionally, when CONFIG_SOC_IMX6 is enabled. The actual code is three instructions long, so it's arguably ok to just leave it in for all i.MX6 kernel configurations. Fixes: 05136f0897b5 ("ARM: imx: support arm power off in cpuidle for i.mx6sx") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159Thomas Gleixner
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-09-17ARM: imx: add suspend/resume support for i.mx6ulAnson Huang
This patch adds suspend function for i.MX6UL, it supports "standby" and "mem" mode, for "standby" mode, SoC will enter STOP mode only, while for "mem" mode, SoC will enter STOP mode and DDR IO will be set to low power mode. As i.MX6UL contains a "Cortex-A7" ARM core which has no PL310, so we need to avoid any PL310 operations during suspend/resume, also, we need to flush Cortex-A7's inernal L2 cache before suspend. Signed-off-by: Anson Huang <b20788@freescale.com>
2014-11-23ARM: imx: replace cpu type check with ddr type checkAnson Huang
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-08-18ARM: imx: fix TLB missing of IOMUXC base address during suspendShawn Guo
After the suspend routine running in OCRAM puts DDR into self-refresh, it will access IOMUXC block to float DDR IO for power saving. A TLB missing of IOMUXC base address may happen in this case, and triggers an access to DDR, and thus hangs the system. The failure is discovered by running suspend/resume on a Cubox-i board. Though the issue is not Cubox-i specific, it can be hit the on the board quite easily with the 3.15 or 3.16 kernel. Fix the issue with a dummy access to IOMUXC block at the beginning of suspend routine, so that the address translation can be filled into TLB before DDR is put into self-refresh. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Cc: <stable@vger.kernel.org> Acked-by: Anson Huang <Anson.Huang@freescale.com>
2014-07-18ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King
ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: imx: convert to common l2c310 early resume functionalityRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-03-05ARM: imx6: move v7_cpu_resume() into suspend-imx6.SShawn Guo
The suspend-imx6.S is introduced recently for suspend low-level assembly code. Since function v7_cpu_resume() is only used by suspend support, it makes sense to move the function into suspend-imx6.S, and control the build of the file with CONFIG_SUSPEND option. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-03-05ARM: imx: add suspend in ocram support for i.mx6slAnson Huang
i.MX6SL's suspend in ocram function is derived from i.MX6Q, it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V, measured on i.MX6SL EVK board, SH5. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-03-05ARM: imx: add suspend in ocram support for i.mx6qAnson Huang
When system enter suspend, we can set the DDR IO to high-Z state to save DDR IOs' power consumption, this operation can save many power(from ~26mA@1.5V to ~15mA@1.5V, measured on i.MX6Q SabreSD board, R25) of DDR IOs. To achieve that, we need to copy the suspend code to ocram and run the low level hardware related code(set DDR IOs to high-Z state) in ocram. If there is no ocram space available, then system will still do suspend in external DDR, hence no DDR IOs will be set to high-Z. The OCRAM usage layout is as below, ocram suspend region(4K currently): ======================== high address ====================== . . . ^ ^ ^ imx6_suspend code PM_INFO structure(imx6_cpu_pm_info) ======================== low address ======================= Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>