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2012-07-05ARM: OMAP2+: Remove unnecessary ifdef around __omap2_set_globalsVaibhav Hiremath
The function __omap2_set_globals() can be common across all platforms/architectures, even in case of omap4, internally it calls same set of functions as in __omap2_set_globals() function (except for sdrc). This patch adds new config flag SOC_HAS_OMAP2_SDRC to handle sdrc, so that we can reuse same function across omap2/3/4... Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-07-05ARM: OMAP2+: am33xx: Change cpu_is_am33xx to soc_is_am33xxVaibhav Hiremath
As per recent discussion on the linux-omap list, we are moving in the direction where, we will have only architecture, ARCH_OMAP2PLUS and all devices/platforms will be treated as a SoC underneath. So the first step in this direction is to adopt this change for all new devices getting in, converting cpu_is_am33xx/335x() ==> soc_is_am33xx/335x() Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-07-05ARM: OMAP2+: am33xx: Make am33xx as a separate classVaibhav Hiremath
Initially, we decided to make am33xx family of device to fall under omap3 class (cpu_is_omap34xx() = true), since it carries Cortex-A8 core. But while adding complete baseport support (like, clock, power and hwmod) support, it is observed that, we are creating more and more problems by treating am33xx device as omap3 family, as nothing matches between them (except cortex-A8 mpu). So, after long discussion we have came to the conclusion that, we should not consider am33xx device as omap3 family, instead create separate class (SOC_AM33XX) under OMAP2PLUS. This means, for am33xx device, cpu_is_omap34xx() will return false, and only cpu_is_am33xx() will be true. Please refer to the link below, for mailing-list discussion on this - http://www.spinics.net/lists/linux-omap/msg69439.html Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: fixed typo, updated for soc_is changes] Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-07-05ARM: OMAP2+: Move omap3 dpll ops to dpll3xxx.cVaibhav Hiremath
In order to remove unnecessary idefs, move noncore and core dpll ops to dpll3xxx.c file (where it should have been already). The clkops (clkops_omap3_core_dpll_ops & clkops_omap3_noncore_dpll_ops) is used in clock data files, and dependency is already handled by Makefile rule. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-07-05Merge tag 'omap-devel-f-for-3.6' of ↵Tony Lindgren
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-part2 Miscellaneous OMAP clock, hwmod, clockdomain, and powerdomain patches for 3.6. Mostly small infrastructure improvements, and preparation for OMAP5 and AM33xx code. Conflicts: arch/arm/mach-omap2/omap_hwmod.c arch/arm/plat-omap/include/plat/omap_hwmod.h
2012-07-04Merge branches 'hwmod_am335x_support_3.6', 'clkdm_pwrdm_devel_a_3.6' and ↵Paul Walmsley
'misc_devel_3.6' into omap_devel_f_3.6
2012-07-04ARM: OMAP2+: hwmod code: add support to set dmadisable in hwmod frameworkKishon Vijay Abraham I
The DMADISABLE bit is a semi-automatic bit present in sysconfig register of some modules. When the DMA must perform read/write accesses, the DMADISABLE bit is cleared by the hardware. But when the DMA must stop for power management, software must set the DMADISABLE bit back to 1. In cases where the ROMCODE/BOOTLOADER uses dma, the hardware clears the DMADISABLE bit (but the romcode/bootloader might not set it back to 1). In order for the kernel to start in a clean state, it is necessary for the kernel to set DMADISABLE bit back to 1 (irrespective of whether it's been set to 1 in romcode or bootloader). During _reset of the (hwmod)device, the DMADISABLE bit is set so that it does not prevent idling of the system. (NOTE: having DMADISABLE to 0, prevents the system to idle) DMADISABLE bit is present in usbotgss module of omap5. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [paul@pwsan.com: updated to apply; fixed checkpatch warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP2+: PRM/CM: Move the stubbed prm and cm functions to prcm.c file ↵R Sricharan
and make them __weak Some prm and cm registers read/write and status functions are built only for some custom OMAP2+ builds and are stubbed in header files for other builds under ifdef statements. But this results in adding new CONFIG_ARCH_OMAPXXX checks when SOCs are added in the future. So move them to a common place for OMAP2+ and make them 'weak' implementations. This way no new ifdefs would be required in the future and also cleans up the existing code. Signed-off-by: R Sricharan <r.sricharan@ti.com> [paul@pwsan.com: unsplit quoted strings; moved PRM functions to mach-omap2/prm_common.c; resolved sparse warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() APITarun Kanti DebBarma
Add an API to get main clock name associated with a given @oh. This will avoid the need to construct fclk names during early initialization in order to get fclk handle using clk_get(). Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP3+: dpll: optimize noncore dpll locking logicVikram Pandita
If the dpll is already locked, code can be optimized to return much earlier than doing redundent set of lock mode and wait on idlest. Cc: Tony Lindgren <tony@atomide.com> Cc: Jon Hunter <jon-hunter@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP3: control: add definition for CONTROL_CAMERA_PHY_CTRLSakari Ailus
The register is used to configure the behaviour of the CSI-2 and CCP-2 receivers. This register is available only in OMAP3630. The original patch was submitted by Vimarsh Zutshi. Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Cc: Vimarsh Zutshi <vimarsh.zutshi@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP2+: powerdomain code: Fix Wake-up power domain power statusJon Hunter
The wake-up power domain is an alway-on power domain and so this power domain does not have a power state status (PM_PWSTST_xxx) register that indicates the current state. However, during the registering of the wake-up power domain the state of the domain is queried by calling pwrdm_read_pwrst(). This actually tries to read a register that does not exist and returns a value of 0 that indicates that the current state is OFF. The OFF state count of the wake-up power domain is then set to 1 and the current state to OFF. Both of which are incorrect. To fix this, if a power domain only supports the ON state, do not attempt to read the power state status register and simply return ON as the current power state. This is based upon Tony's current linux-omap master branch. Testing: - Boot tested on OMAP4460 panda. - Boot tested on OMAP3430 beagle and validated CORE RET still working (using Paul's 32k timer patch [1]). [1] http://marc.info/?l=linux-omap&m=134000053229888&w=2 Signed-off-by: Jon Hunter <jon-hunter@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [paul@pwsan.com: edited commit message slightly] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP4: clockdomain/CM code: Update supported transition modesJon Hunter
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the following transition modes ... NO_SLEEP (0x0) - A clock domain sleep transition is never initiated, irrespective of the hardware conditions. SW_SLEEP (0x1) - A software-forced sleep transition. The transition is initiated when the associated hardware conditions are satisfied SW_WKUP (0x2) - A software-forced clock domain wake-up transition is initiated, irrespective of the hardware conditions. HW_AUTO (0x3) - Hardware-controlled automatic sleep and wake-up transition is initiated by the PRCM module when the associated hardware conditions are satisfied. For OMAP4 devices, SW_SLEEP is equivalent to HW_AUTO and NO_SLEEP is equivalent to SW_WKUP. The only difference between HW_AUTO and SW_SLEEP for OMAP4 devices is that the PRM_IRQSTATUS_MPU.TRANSITION_ST interrupt status is set in case of SW_SLEEP transition, and not set in case of HW_AUTO transition. For OMAP4 devices, all CLKDMs support HW_AUTO and therefore we can place the CLKDMs in the HW_AUTO state instead of the SW_SLEEP mode. Hence, we do not need to use the SW_SLEEP mode. With regard to NO_SLEEP and SW_WKUP it is preferred to use SW_WKUP mode if the CLKDM supports it and so use this mode instead of NO_SLEEP where possible. For a software perspective the above 4 modes are represented by the following flags to indicate what modes are supported by each of the CLKDMs. CLKDM_CAN_DISABLE_AUTO --> NO_SLEEP CLKDM_CAN_ENABLE_AUTO --> HW_AUTO CLKDM_CAN_FORCE_SLEEP --> SW_SLEEP CLKDM_CAN_FORCE_WAKEUP --> SW_WKUP By eliminating the SW_SLEEP mode the the mapping of the flags for OMAP4 devices can becomes ... CLKDM_CAN_DISABLE_AUTO --> NO_SLEEP CLKDM_CAN_ENABLE_AUTO --> HW_AUTO CLKDM_CAN_FORCE_SLEEP --> HW_AUTO CLKDM_CAN_FORCE_WAKEUP --> SW_WKUP Cc: Ming Lei <ming.lei@canonical.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xxVaibhav Hiremath
In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined, sysc_type3: | 3 2 | 1 0 | | STDBYMODE | IDLEMODE | So introduce new sysc_type3 in omap_hwmod common data. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-07-04Merge tags 'omap-cleanup-for-v3.6', 'omap-devel-dmtimer-for-v3.6' and ↵Tony Lindgren
'omap-devel-am33xx-for-v3.6' into devel-am33xx-part2
2012-06-28Merge branch 'cleanup-hwmod' into cleanupTony Lindgren
Conflicts: arch/arm/mach-omap2/dsp.c
2012-06-28Merge branches 'cleanup-udc' and 'cleanup-dma' into cleanupTony Lindgren
2012-06-27ARM: OMAP4470: Fix OMAP4470 boot failureJon Hunter
OMAP4470 currently fails to boot, printing various messages such as ... omap_hwmod: mpu: cannot clk_get main_clk dpll_mpu_m2_ck omap_hwmod: mpu: cannot _init_clocks ------------[ cut here ]------------ WARNING: at arch/arm/mach-omap2/omap_hwmod.c:2062 _init+0x2a0/0x2e4() omap_hwmod: mpu: couldn't init clocks Modules linked in: [<c001c7fc>] (unwind_backtrace+0x0/0xf4) from [<c0043c64>] (warn_slowpath_common+0x4c/0x64) [<c0043c64>] (warn_slowpath_common+0x4c/0x64) from [<c0043d10>] (warn_slowpath_fmt+0x30/0x40) [<c0043d10>] (warn_slowpath_fmt+0x30/0x40) from [<c0674208>] (_init+0x2a0/0x2e4) [<c0674208>] (_init+0x2a0/0x2e4) from [<c067428c>] (omap_hwmod_setup_one+0x40/0x60) [<c067428c>] (omap_hwmod_setup_one+0x40/0x60) from [<c0674280>] (omap_hwmod_setup_one+0x34/0x60) [<c0674280>] (omap_hwmod_setup_one+0x34/0x60) from [<c06726f4>] (omap_dm_timer_init_one+0x30/0x250) [<c06726f4>] (omap_dm_timer_init_one+0x30/0x250) from [<c0672930>] (omap2_gp_clockevent_init+0x1c/0x108) [<c0672930>] (omap2_gp_clockevent_init+0x1c/0x108) from [<c0672c60>] (omap4_timer_init+0x10/0x5c) [<c0672c60>] (omap4_timer_init+0x10/0x5c) from [<c066c418>] (time_init+0x20/0x30) [<c066c418>] (time_init+0x20/0x30) from [<c0668814>] (start_kernel+0x1b0/0x304) [<c0668814>] (start_kernel+0x1b0/0x304) from [<80008044>] (0x80008044) ---[ end trace 1b75b31a2719ed1c ]--- The problem is that currently none of the clocks are being registered for OMAP4470 devices and so on boot-up no clocks can be found and the kernel panics. This fix allows the kernel to boot without failure using a simple RAMDISK file system on OMAP4470 blaze board. Per feedback from Paul and Benoit the 4470 clock data is incomplete for new modules such as the 2D graphics block that has been added to the 4470. Therefore add a warning to indicate that the clock data is incomplete. Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> [tony@atomide.com: updated comments] Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-26ARM: OMAP2+: nand: fix build error when CONFIG_MTD_ONENAND_OMAP2=nKevin Hilman
commit 8259573b (ARM: OMAP2+: nand: Make board_onenand_init() visible to board code) broke the build for configs with OneNAND disabled. By removing the static in the header file, it created a duplicate definition in the .c and the .h files, resuling in a build error: /work/kernel/omap/dev/arch/arm/mach-omap2/board-flash.c:102:111: error: redefinition of 'board_onenand_init' /work/kernel/omap/dev/arch/arm/mach-omap2/board-flash.h:56:51: note: previous definition of 'board_onenand_init' was here make[2]: *** [arch/arm/mach-omap2/board-flash.o] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [arch/arm/mach-omap2] Error 2 make: *** [sub-make] Error 2 Fix this by removing the duplicate dummy entry from the C file. Cc: Enric Balletbò i Serra <eballetbo@gmail.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-23Merge tag 'omap-fixes-a-for-3.5rc' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes From Paul Walmsley (as per Tony Lindgren's request): "Some uncontroversial OMAP clock, hwmod, and compiler warning fixes for 3.5-rc" * tag 'omap-fixes-a-for-3.5rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending: ARM: OMAP4: hwmod data: Force HDMI in no-idle while enabled ARM: OMAP2+: mux: fix sparse warning ARM: OMAP2+: CM: increase the module disable timeout ARM: OMAP4: clock data: add clockdomains for clocks used as main clocks ARM: OMAP4: hwmod data: fix 32k sync timer idle modes ARM: OMAP4+: hwmod: fix issue causing IPs not going back to Smart-Standby ARM: OMAP: PM: Lock clocks list while generating summary
2012-06-23Merge tag 'omap-fixes-for-v3.5-rc3' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes From Tony Lindgren: "Here are a few fixes with the biggest one being fix for Beagle DVI reset. All of them are regression fixes, except for the missing omap2 interrupt controller binding that somehow got missed earlier." * tag 'omap-fixes-for-v3.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: Fix Beagleboard DVI reset gpio arm/dts: OMAP2: Fix interrupt controller binding ARM: OMAP2: Fix tusb6010 GPIO interrupt for n8x0 ARM: OMAP2+: Fix MUSB ifdefs for platform init code
2012-06-21ARM: OMAP4: hwmod data: Force HDMI in no-idle while enabledRicardo Neri
As per the OMAP4 documentation, audio over HDMI must be transmitted in no-idle mode. This patch adds the HWMOD_SWSUP_SIDLE so that omap_hwmod uses no-idle/force-idle settings instead of smart-idle mode. This is required as the DSS interface clock is used as functional clock for the HDMI wrapper audio FIFO. If no-idle mode is not used, audio could be choppy, have bad quality or not be audible at all. Signed-off-by: Ricardo Neri <ricardo.neri@ti.com> [b-cousson@ti.com: Update the subject and align the .flags location with the script template] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-21ARM: OMAP2+: mux: fix sparse warningPaul Walmsley
Commit bbd707acee279a61177a604822db92e8164d00db ("ARM: omap2: use machine specific hook for late init") resulted in the addition of this sparse warning: arch/arm/mach-omap2/mux.c:791:12: warning: symbol 'omap_mux_late_init' was not declared. Should it be static? Fix by including the header file containing the prototype. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Tony Lindgren <tony@atomide.com>
2012-06-21ARM: OMAP2+: CM: increase the module disable timeoutPaul Walmsley
Increase the timeout for disabling an IP block to five milliseconds. This is to handle the usb_host_fs idle latency, which takes almost four milliseconds after a host controller reset. This is the second of two patches needed to resolve the following boot warning: omap_hwmod: usb_host_fs: _wait_target_disable failed Thanks to Sergei Shtylyov <sshtylyov@mvista.com> for finding an unrelated hunk in a previous version of this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Tero Kristo <t-kristo@ti.com>
2012-06-21ARM: OMAP4: clock data: add clockdomains for clocks used as main clocksPaul Walmsley
Until the OMAP4 code is converted to disable the use of the clock framework-based clockdomain enable/disable sequence, any clock used as a hwmod main_clk must have a clockdomain associated with it. This patch populates some clock structure clockdomain names to resolve the following warnings during kernel init: omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck. omap_hwmod: trace_clk_div_ck: missing clockdomain for trace_clk_div_ck. omap_hwmod: l3_div_ck: missing clockdomain for l3_div_ck. omap_hwmod: ddrphy_ck: missing clockdomain for ddrphy_ck. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoît Cousson <b-cousson@ti.com>
2012-06-21ARM: OMAP4: hwmod data: fix 32k sync timer idle modesPaul Walmsley
The 32k sync timer IP block target idle modes in the hwmod data are incorrect. The IP block does not support any smart-idle modes. Update the data to reflect the correct modes. This problem was initially identified and a diff fragment posted to the lists by Benoît Cousson <b-cousson@ti.com>. A patch description bug in the first version was also identified by Benoît. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Tero Kristo <t-kristo@ti.com>
2012-06-21ARM: OMAP4+: hwmod: fix issue causing IPs not going back to Smart-StandbyDjamil Elaidi
If an IP is configured in Smart-Standby-Wakeup, when disabling wakeup feature the IP will not go back to Smart-Standby, but will remain in Smart-Standby-Wakeup. Signed-off-by: Djamil Elaidi <d-elaidi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-20Merge branches 'clock_cleanup_misc_3.6', ↵Paul Walmsley
'control_clean_dspbridge_writes_cleanup_3.6', 'hwmod_soc_conditional_cleanup_3.6', 'mcbsp_clock_aliases_cleanup_3.6' and 'remove_clkdm_requirement_from_hwmod_3.6' into omap_cleanup_a_3.6 Conflicts: arch/arm/mach-omap2/omap_hwmod.c
2012-06-20ARM: OMAP: Fix Beagleboard DVI reset gpioRuss Dill
Commit e813a55eb9c9bc6c8039fb16332cf43402125b30 ("OMAP: board-files: remove custom PD GPIO handling for DVI output") moved TFP410 chip's powerdown-gpio handling from the board files to the tfp410 driver. One gpio_request_one(powerdown-gpio, ...) was mistakenly left unremoved in the Beagle board file. This causes the tfp410 driver to fail to request the gpio on Beagle, causing the driver to fail and thus the DVI output doesn't work. This patch removes several boot errors from board-omap3beagle.c: - gpio_request: gpio--22 (DVI reset) status -22 - Unable to get DVI reset GPIO There is a combination of leftover code and revision confusion. Additionally, xM support is currently a hack. For original Beagleboard this removes the double initialization of GPIO 170, properly configures it as an output, and wraps the initialization in an if block so that xM does not attempt to request it. For Beagleboard xM it removes reference to GPIO 129 which was part of rev A1 and A2 designs, but never functioned. It then properly assigns beagle_dvi_device.reset_gpio in beagle_twl_gpio_setup and removes the hack of initializing it high. Additionally, it uses gpio_set_value_cansleep since this GPIO is connected through i2c. Unfortunately, there is no way to tell the difference between xM A2 and A3. However, GPIO 129 does not function on rev A1 and A2, and the TWL GPIO used on A3 and beyond is not used on rev A1 and A2, there are no problems created by this fix. Tested on Beagleboard-xM Rev C1 and Beagleboard Rev B4. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-20ARM: OMAP2: Fix tusb6010 GPIO interrupt for n8x0Tony Lindgren
Here's one more gpio_to_irq conversion that we missed earlier. Tested with n800 in gadget mode using USB_ETH. Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-20ARM: OMAP2+: Fix MUSB ifdefs for platform init codeTony Lindgren
Commit 62285963 (usb: musb: drop a gigantic amount of ifdeferry) got rid of a bunch of ifdefs in the MUSB code. Looks like the platform init code is still using these dropped defines though, which in many cases results the board defaulting always to host mode. Currently the situation is that USB_MUSB_HDRC is the main Kconfig option with additional USB_GADGET_MUSB_HDRC so only these two should be used to select between host and OTG mode. Fix the situation for omaps. The following users should fix the platform init code in a similar way: Dropped Kconfig option Current users USB_MUSB_OTG blackfin, davinci, not in Kconfigs USB_MUSB_PERIPHERAL davinci, not in Kconfigs USB_MUSB_HOST davinci, not in Kconfigs USB_MUSB_HDRC_HCD blackfin, not in Kconfigs USB_MUSB_OTG blackfin, not in Kconfigs Cc: Mike Frysinger <vapier@gentoo.org> Cc: Sekhar Nori <nsekhar@ti.com> Cc: linux-usb@vger.kernel.org Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-19ARM: OMAP2+: hwmod: remove prm_clkdm, cm_clkdm; allow hwmods to have no ↵Paul Walmsley
clockdomain Remove prm_clkdm and cm_clkdm and allow hwmods to have no clockdomain. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
2012-06-18ARM: OMAP3: Move McBSP fck clock alias to hwmod dataPeter Ujfalusi
Remove the existing alias for pad_fck, prcm_fck from the clock data and add them as opt_clks to the hwmod data. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2: Move McBSP fck clock alias to hwmod data for OMAP2430Peter Ujfalusi
Remove the existing alias for pad_fck, prcm_fck from the clock data and add them as opt_clks to the hwmod data. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2: Move McBSP fck clock alias to hwmod data for OMAP2420Peter Ujfalusi
Remove the existing alias for pad_fck, prcm_fck from the clock data and add them as opt_clks to the hwmod data. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP: dsp: interface to control module functionsOmar Ramirez Luna
Provide an interface for a driver to call SCM functions to set a boot address and boot mode. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2+: control: new APIs to configure boot address and modeOmar Ramirez Luna
SCM contains boot addr and boot mode registers to control other processors on different OMAP versions. It controls the boot address and mode for DSP based subsystems like: IVA 2.1 (OMAP2430), IVA 2.2 (OMAP3) and DSP (OMAP4). If contained within SCM registers, when a processor is booting it uses BOOTADDR to start running the code at that location. BOOTMOD register specifies a different set of modes for the processor to execute when booting (from direct, idle, self-loop, user and default). Since there was no offset associated with OMAP4, this patch defines it. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2+: hwmod: use init-time function pointer for _init_clkdmKevin Hilman
Rather than use runtime cpu_is* checking inside _init_clkdm, initialize SoC specific function pointer at init time. Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: convert to use soc_ops function pointers; remove second para from commit message since soc_ops function pointers are now set during hwmod layer init] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2+: hwmod: use init-time function pointer for hardresetKevin Hilman
Rather than using cpu_is* checking at runtime, initialize SoC specific function pointers for the various hard reset functions at init time. Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: convert to use soc_ops function pointers; add kerneldoc] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2+: hwmod: use init-time function pointer for wait_target_readyKevin Hilman
Rather than using cpu_is* checking at runtime, initialize an SoC specific function pointer for wait_target_ready(). While here, downgrade the BUG() to a WARN_ON() so it gives a noisy warning instead of causing a kernel panic. Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: convert to use soc_ops function pointers; add kerneldoc; move soc_ops functions to their own section in the code; integrated the _wait_target_ready() function with the OMAP2/OMAP4 variants; renamed the wait_module_ready field to wait_target_ready] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP4: hwmod: drop extra cpu_is check from _wait_target_disable()Kevin Hilman
_omap4_wait_target_disable() is called only from inside _omap4_disable_module() which is already protected by SoC specific checks. Remove the cpu_is check here. Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-06-18ARM: OMAP2+: hwmod: use init-time function ptrs for enable/disable moduleKevin Hilman
The enable/disable module functions are specific to SoCs with OMAP4-class PRCM. Rather than use cpu_is* checks at runtime inside the enable/disable module functions, use cpu_is at init time to initialize function pointers only for SoCs that need them. NOTE: the cpu_is* check for _enable_module was different than the one for _disable_module, and this patch uses cpu_is_omap44xx() for both. Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: moved soc_ops function pointers to be per-kernel rather than per-hwmod since they do not vary by hwmod; added kerneldoc] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP4: hwmod: rename _enable_module to _omap4_enable_module()Kevin Hilman
_enable_module is specific to SoCs with PRCM interfaces similar to that of the OMAP4, so rename it to be consistent with the corresponding _omap4_disable_module. Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: tweaked commit message] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP AM33xx: clockdomains: Add clockdomain data and respective operationsVaibhav Hiremath
AM33XX PRCM module consists of various clockdomains, in all total we have 18 clockdomains available, with following controlling options, - SW Sleep: sw forced sleep transition - SW Wakeup: sw forced wakeup transition This patch adds all available clockdomain data, respective clockdomain operations for AM33XX family of device, and also integrates it into existing OMAP framework. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> CC: Tony Lindgren <tony@atomide.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: removed CLKDM_NO_AUTODEPS from clockdomain flags, removed unnecessary .clktrctrl_offs field; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP AM33xx: powerdomains: add AM335x supportVaibhav Hiremath
Add offset & mask fields to struct powerdomain In case of AM33xx family of devices, there is no consistency between PWRSTCTRL & PWRSTST register offsers in PRM space, for example - PRM_XXX PWRSTCTRL PWRSTST ======================================= PRM_PER_MOD: 0x0C, 0x08 PRM_WKUP_MOD: 0x04, 0x08 PRM_MPU_MOD: 0x00, 0x04 PRM_DEVICE_MOD: NA, NA And also, there is no consistency between bit-offsets inside PWRSTCTRL & PWRSTST register, for example - PRM_XXX LOGICRET MEMON MEMRET ======================================= GFX_PWRCTRL: 2, 17, 6 PER_PWRCTRL: 3, 25, 29 MPU_PWRCTRL: 2, 18, 22 WKUP_PWRCTRL: 3, NA, NA This means, we need to maintain and pass on all this information in powerdomain handle; so adding fields for, - PWRSTCTRL/ST register offset - Logic retention state mask - mem_on/ret/pwrst/retst mask Currently, this fields is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support"; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP AM33xx: CM: Introduce AM33xx CM APIs and register level detailsVaibhav Hiremath
As far as PRM/CM/PRCM modules are concerned, AM33XX device is different than OMAP3 and OMAP4 architectures; so similar to PRM implementation, handle AM33XX CM separately. This patch introduces AM33XX CM module low-level api's, used and required by omap clockdomain and hwmod framework. Please note that cm-regbits-33xx.h (register bit field offset) and cm33xx.h (register addr offset) files are mostly auto generated. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> CC: Tony Lindgren <tony@atomide.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split the hwmod code changes in this patch into a separate patch; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP AM33xx: PRM: add PRM supportVaibhav Hiremath
As far as PRM/CM/PRCM modules are concerned, AM33XX device is different than OMAP3 and OMAP4 architectures; so we need to handle it separately. This patch adds support for the PRM APIs required for AM33XX device. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: separated the PRM parts of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support" into this patch; fixed Makefile prm33xx.o location; cleaned up some checkpatch violations; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP AM33xx: voltagedomain: Add voltage domain dataVaibhav Hiremath
Currently dummy voltage domain data is being created in order to succeed boot process, nothing has been done w.r.t actual hardware (voltage control). Also, hook up the AM33XX voltage domain to OMAP framework. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18ARM: OMAP2+: control: Add AM33XX control reg & sec clkctrl offsetVaibhav Hiremath
Define AM33XX control register, in order to allow access to control register address space, also add CONTROL_SEC_CLK_CTRL register offset; both are required in clock tree data, for wdt0 and timer0 clock source select configuration. CONTROL.SEC_CLK_CTRL register is provided to select/configure clock input for WDT0 and TIMER0. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> [paul@pwsan.com: added include of plat/am33xx.h to fix build break; added AM33XX_CONTROL_STATUS bitfields that will be needed for the clock tree; fixed some control.h whitespace problems while here] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-17Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A bit larger set than usual, unfortunately -- I've been sitting on them longer than I meant to so it's really more like 2 -rc pull requests in one, volume-wise. Nearly everything is fixes for fallout from the merge window, or other fixes for bugs. The one exception is the highbank L2-enablement patch, but it was contained enough that I picked it up anyway: - i.MX fixes, mostly for clock and pinctrl changes - OMAP fixes, mostly PM-related - A patch to enable L2 on highbank - A couple of fixes for PXA, Kirkwood, Versatile" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits) ARM: Kirkwood: Fix clk problems modular ethernet driver arm: versatile: fix and enable PCI I/O space ARM: highbank: Add smc calls to enable/disable the L2 ARM i.MX imx21ads: Fix overlapping static i/o mappings ARM: imx6: exit coherency when shutting down a cpu ARM: mx51: Add pinctrl_provide_dummies() ARM: mx31: Add pinctrl_provide_dummies() ARM: OMAP2+: Fix compile for CONFIG_TIDSPBRIDGE platform init code ARM: OMAP3: Fix omap3_l3_block_irq warning when CONFIG_BUG is not set ARM: OMAP: Fix MMC_OMAP build when only MMC_OMAP_HS is selected OMAP2+: UART: Add mechanism to probe uart pins and configure rx wakeup ARM: mmp: fix missing cascade_irq in irq handler ARM: dts: update memory size on brownstone ARM i.MX27 Visstrim M10: fix gpio handling. ARM i.MX53: Fix PLL4 base address ARM i.MX pllv2: make round_rate accurate ARM i.MX pllv2: use standard register set unconditionally ARM: OMAP: Fix lis3lv02d accelerometer to use gpio_to_irq ARM: imx: only call l2x0_init if it's available ARM: imx: only specify i2c device type once ...
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