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fsl,tmu-calibration contains cell pairs (u32-matrix). Mark them as such.
Use matching property syntax and allow correct validation.
No functional changes.
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Per qoriq-thermal.yaml, 'big-endian' is not a valid property.
When the 'little-endian' property is absent, the default is big endian.
Remove it to fix the following schema warning:
tmu@1f00000: 'big-endian' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This adds an appropriate SFP node for Trust Architecture 2.1 devices.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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dma-controller is preferred for dma node.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml:
soc: pcie@3400000:reg:0: \
[0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Crypto engine (CAAM) on LS1012A platform is configured HW-coherent,
mark accordingly the DT node.
Lack of "dma-coherent" property for an IP that is configured HW-coherent
can lead to problems, similar to what has been reported for LS1046A.
Cc: <stable@vger.kernel.org> # v4.12+
Fixes: 85b85c569507 ("arm64: dts: ls1012a: add crypto node")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Now that we have constants, use them. This is just a mechanical change.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Update the calibration table to make the temperature more accurate.
Three platforms have been updated: ls1012a, ls1043a and ls1046a.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The dtschema expects watchdog device node name to be "watchdog":
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: wdog@2ad0000:
$nodename:0: 'wdog@2ad0000' does not match '^watchdog(@.*|-[0-9a-f])?$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add label to pcie nodes so that they are easy to
refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The patch adds ftm_alarm0 DT node
- add new rcpm node
- add ftm_alarm0 node
- aliases ftm_alarm0 as rtc1
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS,
LS1012A-FRDM and LS1012A-FRWY boards.
LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only
one can be accessed at a time.
LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M.
LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M.
Use generic compatibles as "jedec,spi-nor" for automatic detection of
flash. Configure RX and TX buswidth values as 2 as only two I/O lines are
available for data transfer.
Add ls1012a(si) node alongwith flash nodes.
Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Consolidate _HPP/_HPX stuff in pci-acpi.c and simplify it
(Krzysztof Wilczynski)
- Fix incorrect PCIe device types and remove dev->has_secondary_link
to simplify code that deals with upstream/downstream ports (Mika
Westerberg)
- After suspend, restore Resizable BAR size bits correctly for 1MB
BARs (Sumit Saxena)
- Enable PCI_MSI_IRQ_DOMAIN support for RISC-V (Wesley Terpstra)
Virtualization:
- Add ACS quirks for iProc PAXB (Abhinav Ratna), Amazon Annapurna
Labs (Ali Saidi)
- Move sysfs SR-IOV functions to iov.c (Kelsey Skunberg)
- Remove group write permissions from sysfs sriov_numvfs,
sriov_drivers_autoprobe (Kelsey Skunberg)
Hotplug:
- Simplify pciehp indicator control (Denis Efremov)
Peer-to-peer DMA:
- Allow P2P DMA between root ports for whitelisted bridges (Logan
Gunthorpe)
- Whitelist some Intel host bridges for P2P DMA (Logan Gunthorpe)
- DMA map P2P DMA requests that traverse host bridge (Logan
Gunthorpe)
Amazon Annapurna Labs host bridge driver:
- Add DT binding and controller driver (Jonathan Chocron)
Hyper-V host bridge driver:
- Fix hv_pci_dev->pci_slot use-after-free (Dexuan Cui)
- Fix PCI domain number collisions (Haiyang Zhang)
- Use instance ID bytes 4 & 5 as PCI domain numbers (Haiyang Zhang)
- Fix build errors on non-SYSFS config (Randy Dunlap)
i.MX6 host bridge driver:
- Limit DBI register length (Stefan Agner)
Intel VMD host bridge driver:
- Fix config addressing issues (Jon Derrick)
Layerscape host bridge driver:
- Add bar_fixed_64bit property to endpoint driver (Xiaowei Bao)
- Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC drivers separately
(Xiaowei Bao)
Mediatek host bridge driver:
- Add MT7629 controller support (Jianjun Wang)
Mobiveil host bridge driver:
- Fix CPU base address setup (Hou Zhiqiang)
- Make "num-lanes" property optional (Hou Zhiqiang)
Tegra host bridge driver:
- Fix OF node reference leak (Nishka Dasgupta)
- Disable MSI for root ports to work around design problem (Vidya
Sagar)
- Add Tegra194 DT binding and controller support (Vidya Sagar)
- Add support for sideband pins and slot regulators (Vidya Sagar)
- Add PIPE2UPHY support (Vidya Sagar)
Misc:
- Remove unused pci_block_cfg_access() et al (Kelsey Skunberg)
- Unexport pci_bus_get(), etc (Kelsey Skunberg)
- Hide PM, VC, link speed, ATS, ECRC, PTM constants and interfaces in
the PCI core (Kelsey Skunberg)
- Clean up sysfs DEVICE_ATTR() usage (Kelsey Skunberg)
- Mark expected switch fall-through (Gustavo A. R. Silva)
- Propagate errors for optional regulators and PHYs (Thierry Reding)
- Fix kernel command line resource_alignment parameter issues (Logan
Gunthorpe)"
* tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (112 commits)
PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCI
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
arm64: tegra: Add configuration for PCIe C5 sideband signals
PCI: tegra: Add support to enable slot regulators
PCI: tegra: Add support to configure sideband pins
PCI: vmd: Fix shadow offsets to reflect spec changes
PCI: vmd: Fix config addressing when using bus offsets
PCI: dwc: Add validation that PCIe core is set to correct mode
PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver
dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding
PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port
PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port
PCI: Add ACS quirk for Amazon Annapurna Labs root ports
PCI: Add Amazon's Annapurna Labs vendor ID
MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer
PCI: hv: Use bytes 4 and 5 from instance ID as the PCI domain numbers
dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
dt-bindings: PCI: tegra: Add sideband pins configuration entries
PCI: tegra: Add Tegra194 PCIe support
PCI: Get rid of dev->has_secondary_link flag
...
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Remove the num-lanes property to avoid the driver setting the
link width.
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected SerDes
protocol in the RCW (Reset Configuration Word).
The PCIe link training is completed automatically through the selected
SerDes protocol - the link width set-up is updated by hardware after
power on reset, so the num-lanes property is not needed for Layerscape
PCIe.
The current num-lanes property was added erroneously, which actually
indicates the maximum lanes the PCIe controller can support up to,
instead of the lanes assigned to the PCIe controller. The link width set
by SerDes protocol will be overridden by the num-lanes property, hence
the subsequent re-training will fail when the assigned lanes do not
match the value in the num-lanes property.
Remove the property to fix the issue
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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Ls1012a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Enable PCI-E controller for Oxalis board based on NXP/Freescale LS1012a
SoC available as the Mini PCI-E connector on the bottom side.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add this property to all layerscape platforms to improve USB read write performance.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add num-viewport property for PCIe DT nodes to specify how many
viewports are implemented.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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dtc has new checks for I2C and SPI buses. Fix the SPI bus node names
and warnings in unit-addresses.
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@57: I2C bus unit address format error, expected "53"
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@56: I2C bus unit address format error, expected "52"
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late updates from Olof Johansson:
"A couple of late-merged changes that would be useful to get in this
merge window:
- Driver support for reset of audio complex on Meson platforms. The
audio driver went in this merge window, and these changes have been
in -next for a while (just not in our tree).
- Power management fixes for IOMMU on Rockchip platforms, getting
closer to kexec working on them, including Chromebooks.
- Another pass updating "arm,psci" -> "psci" for some properties that
have snuck in since last time it was done"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
iommu/rockchip: Move irq request past pm_runtime_enable
iommu/rockchip: Handle errors returned from PM framework
arm64: rockchip: Force CONFIG_PM on Rockchip systems
ARM: rockchip: Force CONFIG_PM on Rockchip systems
arm64: dts: Fix various entry-method properties to reflect documentation
reset: imx7: Fix always writing bits as 0
reset: meson: add meson audio arb driver
reset: meson: add dt-bindings for meson-axg audio arb
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The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".
commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.
Fix the cpu-capacity.txt documentation that uses the incorrect value so
we don't get copy-paste errors like these. Clarify the language in
idle-states.txt by removing the reference to the psci bindings that
might be causing this confusion.
Finally, fix devicetrees of various boards to reflect current
documentation.
[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Replace license text with corresponding SPDX identifiers and update the
format of existing SPDX identifiers to follow the new guideline
Documentation/process/license-rules.rst.
Note that some of the files mentioned X11 license previously but the
license text actually matches MIT license.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Use '-' instead of '_' to fix the following DTC warnings with W=1:
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-'
Cc: Harninder Rai <harninder.rai@nxp.com>
Cc: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Cc: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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According to PSCI standard v0.2, for CPU_SUSPEND call, which is
used by cpu idle framework, bit[16] of state parameter must be 0.
So update bit[16] of property 'arm,psci-suspend-param', which is
used as state parameter, to 0.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Move cpu_thermal node from soc node to root node.
cpu_thermal node does not have any register properties and thus
shouldn't be placed on the bus.
This fixes the following build warnings with W=1:
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"We add device tree files for a couple of additional SoCs in various
areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
networking, Amlogic A113D for audio, and Renesas R-Car V3M for
automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
Amlogic and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues
that the latest version of 'dtc' now warns about. Unfortunately there
is still a lot left to do.
A rework of the ARM foundation model introduced several new files for
common variations of the model"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
dt-bindings: bus: Add documentation for the Technologic Systems NBUS
arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
ARM: dts: owl-s500: Add CubieBoard6
dt-bindings: arm: actions: Add CubieBoard6
ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
arm: dts: mt7623: remove unused compatible string for pio node
arm: dts: mt7623: update usb related nodes
arm: dts: mt7623: update crypto node
ARM: dts: sun8i: a711: Enable USB OTG
ARM: dts: sun8i: a711: Add regulator support
ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
ARM: dts: sunxi: Add dtsi for AXP81x PMIC
arm64: dts: allwinner: H5: Restore EMAC changes
...
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Add PCIe controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
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Add MSI controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
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Add optee device tree node on ls1012a, ls1043a, ls1046a, ls1088a
and ls208xa.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS1012A has one USB 3.0(DWC3) controller and
one USB 2.0 controller.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Accordingly, update the clock-frequency in sysclk to 125M as platform
input clock.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There are two eSDHC controllers in LS1012A. This patch is to add
eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS1012A has a SEC v5.4 security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There is a thermal monitoring unit on ls1012a soc which can
monitor and record the temperature of cores so that appropriate actions
can be taken or alarm the user when the temperature exceeds a programmed
temperature threshold.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Updated sata node to add ecc register address and dma coherence
property.
Enable sata on ls1012a platforms as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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