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2019-08-22arm64: dts: fsl: Remove num-lanes property from PCIe nodesHou Zhiqiang
Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-03-22arm64: dts: ls1043a: add crypto node alias also for qdsHoria Geantă
crypto node alias is needed by U-boot to identify the node and perform fix-ups, like adding "fsl,sec-era" property or deleting a job ring child node (in case ARM TF-A is running). Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-22arm64: dts: fsl: Remove unused properties from FSL QSPI nodesFrieder Schrempf
After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 nodeRan Wang
Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11arm64: dts: layerscape: add num-viewport property for PCIe DT nodesHou Zhiqiang
Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: ls1043a: add qdma device tree nodesPeng Ma
add the qDMA device tree nodes for LS1043A devices. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: layerscape: removed compatible string "snps,dw-pcie"Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add the status property disable PCIeBao Xiaowei
Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-26arm64: dts: fsl: Fix I2C and SPI bus warningsRob Herring
dtc has new checks for I2C and SPI buses. Fix the SPI bus node names and warnings in unit-addresses. arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@57: I2C bus unit address format error, expected "53" arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@56: I2C bus unit address format error, expected "52" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Li Yang <leoyang.li@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03arm64: dts: fsl: remove big-endian field from IFC controllerPrabhakar Kushwaha
As per IFC binding, Absence of "little-endian" field causes registers access in big-endian mode. So no need to set explicit big-endian field IFC node for LS1043A and LS1046A. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-08-25Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "A couple of late-merged changes that would be useful to get in this merge window: - Driver support for reset of audio complex on Meson platforms. The audio driver went in this merge window, and these changes have been in -next for a while (just not in our tree). - Power management fixes for IOMMU on Rockchip platforms, getting closer to kexec working on them, including Chromebooks. - Another pass updating "arm,psci" -> "psci" for some properties that have snuck in since last time it was done" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: iommu/rockchip: Move irq request past pm_runtime_enable iommu/rockchip: Handle errors returned from PM framework arm64: rockchip: Force CONFIG_PM on Rockchip systems ARM: rockchip: Force CONFIG_PM on Rockchip systems arm64: dts: Fix various entry-method properties to reflect documentation reset: imx7: Fix always writing bits as 0 reset: meson: add meson audio arb driver reset: meson: add dt-bindings for meson-axg audio arb
2018-08-24arm64: dts: Fix various entry-method properties to reflect documentationAmit Kucheria
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Fix the cpu-capacity.txt documentation that uses the incorrect value so we don't get copy-paste errors like these. Clarify the language in idle-states.txt by removing the reference to the psci bindings that might be causing this confusion. Finally, fix devicetrees of various boards to reflect current documentation. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-03arm64: dts: freescale: Add missing cooling device properties for CPUsViresh Kumar
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19arm64: dts: freescale: Update to use SPDX identifiersLi Yang
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-24arm64: dts: fsl: update the cpu idle nodeYuantian Tang
According to PSCI standard v0.2, for CPU_SUSPEND call, which is used by cpu idle framework, bit[16] of state parameter must be 0. So update bit[16] of property 'arm,psci-suspend-param', which is used as state parameter, to 0. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-24arm64: dts: ls1043a: add cpu idle supportYuantian Tang
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12arm64: dts: ls1043a: Move cpu_thermal out of bus nodeFabio Estevam
Move cpu_thermal node from soc node to root node. cpu_thermal node does not have any register properties and thus shouldn't be placed on the bus. This fixes the following build warnings with W=1: arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-10-13arm64: dts: update the DPAA QBMan nodesMadalin Bucur
Use constants in the interrupt description. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-09-22arm64: dts: ls: Add optee nodeSumit Garg
Add optee device tree node on ls1012a, ls1043a, ls1046a, ls1088a and ls208xa. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-08-31arm64: dts: ls1043a: Share all MSIsMinghuan Lian
In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes "msi-parent" to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-08-31arm64: dts: ls1043a: Fix typo of MSI compatible stringMinghuan Lian
"1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-21arm64: dts: add LS1043A DPAA FMan supportMadalin Bucur
Add the DPAA 1.x FMan device tree nodes for LS1043A boards. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-16arm64: dts: add LS1043A DPAA QBMan nodesMadalin Bucur
Add the DPAA 1.x QMan and BMan nodes in the LS1043A device tree. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: Define big endian of IFC for LS1043a/LS1046aPrabhakar Kushwaha
Integrated flash controller present in LS1043A and LS1046A is big endian. So add big endian property in the devive tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: freescale: update the copyright claimsLi Yang
Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-08arm64: dts: added ecc register address to sata node on ls1043aTang Yuantian
For ls1043 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-18Merge tag 'imx-dt64-4.10' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB. * tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-15arm64: dts: ls1043a: Add TMU device tree support for LS1043AHongtao Jia
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-21arm64: dts: Add timer erratum property for LS2080A and LS1043AScott Wood
Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees. Signed-off-by: Scott Wood <oss@buserror.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-14Merge branch 'for-4.9' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: - Write same support added - Minor ahci MSIX irq handling updates - Non-critical SCSI command translation fixes - Controller specific changes * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC" libata: remove <asm-generic/libata-portmap.h> libata: remove unused definitions from <asm/libata-portmap.h> pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR ata: Replace BUG() with BUG_ON(). ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc. libata: Some drives failing on SCT Write Same ahci: use pci_alloc_irq_vectors libata: SCT Write Same handle ATA_DFLAG_PIO libata: SCT Write Same / DSM Trim libata: Add support for SCT Write Same libata: Safely overwrite attached page in WRITE SAME xlat ahci: also use a per-port lock for the multi-MSIX case ARM: dts: STiH407-family: Add ports-implemented property in sata nodes ahci: st: Add ports-implemented property in support ahci: qoriq: enable snoopable sata read and write ahci: qoriq: adjust sata parameter libata-scsi: fix MODE SELECT translation for Control mode page libata-scsi: use u8 array to store mode page copy
2016-09-14Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann
* dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
2016-09-14arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-08-30arm64: dts: Add DDR memory controller for Layerscape SoCsYork Sun
Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-10ahci: qoriq: enable snoopable sata read and writeTang Yuantian
By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-01Merge tag 'armsoc-dt64' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull 64-bit ARM DT updates from Olof Johansson: "Just as the 32-bit contents, the 64-bit device tree branch also contains a number of additions this release cycle. New platforms: - LG LG1313 - Mediatek MT6755 - Renesas r8a7796 - Broadcom 2837 Other platforms with larger updates are: - Nvidia X1 platforms (USB 3.0, regulators, display subsystem) - Mediatek MT8173 (display subsystem added) - Rockchip RK3399 (a lot of new peripherals) - ARM Juno reference implementation (SCPI power domains, coresight, thermal)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1 Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" arm64: dts: hi6220: Add pl031 RTC support arm64: dts: r8a7796/salvator-x: Enable watchdog timer arm64: dts: r8a7796: Add RWDT node arm64: dts: r8a7796: Use SYSC "always-on" PM Domain ...
2016-06-21arm64: dts: ls1043a: Add cache nodes for cacheinfo supportLi Yang
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodesLiu Gang
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-11arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-09arm64: dts: fsl: Update address-cells and reg properties of cpu nodesAlison Wang
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-07arm64: dts: ls1043a: add crypto nodeHoria Geantă
LS1043A has a SEC v5.4 security engine. For now don't add rtic or sec_mon subnodes, since these features haven't been tested yet. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-04-18arm64: dts: ls1043a: add the DTS node for QSPI supportYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodesLiu Gang
The compatible "fsl,qoriq-gpio" is used by gpio driver: drivers/gpio/gpio-mpc8xxx.c to implement general gpio functionalities. The chip-specific compatible "fsl,ls1043a-gpio" may be used to fix potential gpio IP block errata or other chip-specific gpio issues. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-14arm64: dts: ls1043a: Add quirk for Erratum A009116Rajesh Bhagat
Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-22arm64: dts: add Freescale LS1043a SoC supportMingkai Hu
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are similar to LS1021a which also complies to Freescale Chassis 2.1 spec. Created LS1043a SoC DTSI file to be included by board level DTS files. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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