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Per microchip,ksz.yaml, phy-mode is not a valid property in the
top-level switch node.
phy-mode = "rgmii-id" is already passed in the CPU port switch (port@5).
Remove it from the top-level switch node to fix the following
schema warning:
switch@5f: Unevaluated properties are not allowed ('phy-mode' was unexpected)
from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Per gateworks-gsc.yaml, #address-cells and #size-cells are mandatory
properties.
Pass them to fix the following schema warning:
imx8mm-venice-gw7903.dtb: gsc@20: '#address-cells' is a required property
from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
imx8mm-venice-gw7903.dtb: gsc@20: '#size-cells' is a required property
from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This is not used by the DSA dt-binding, so remove it from the devicetrees.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pass "brcm,bcm4329-fmac" to fix the following schema warnings:
imx8mp-venice-gw74xx.dtb: wifi@0: compatible: 'oneOf' conditional failed, one must be fixed:
['cypress,cyw4373-fmac'] is too short
'cypress,cyw4373-fmac' is not one of ['brcm,bcm4329-fmac', 'pci14e4,43dc', 'pci14e4,4464', 'pci14e4,4488', 'pci14e4,4425', 'pci14e4,4433']
from schema $id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
imx8mn-venice-gw7902.dtb: wifi@0: compatible: 'oneOf' conditional failed, one must be fixed:
['brcm,bcm43455-fmac'] is too short
'brcm,bcm43455-fmac' is not one of ['brcm,bcm4329-fmac', 'pci14e4,43dc', 'pci14e4,4464', 'pci14e4,4488', 'pci14e4,4425', 'pci14e4,4433']
from schema $id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pass a single BD71847 clock entry to fix the following schema
warning:
imx8mm-var-som-symphony.dtb: pmic@4b: clocks: [[22], [0]] is too long
from schema $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The GW7901 has a Murata LBEE5H 802.11abgnac / BT5 module based on the
Cypress CYW43455 which supports SDR50/SDR104.
Add dt pinctrl for the 100mhz and 200mhz states to support SDR50/SDR104.
While at it add the dt node for the CYW43455 wifi for the brcmfmac
driver.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add regulator config for cpu-supply in order to support cpufreq.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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On these boards, vdd_bat is 16bit, not 24bit. Reading them as 24bit
values yield garbage values because of the additional byte, which is a
configurable fan trippoint[1].
So set their mode to mode_voltage_16bit = 3 instead of
mode_voltage_24bit = 1.
[1]: http://trac.gateworks.com/wiki/gsc#SystemTemperatureandVoltageMonitor
Only tested on GW7100.
Signed-off-by: Nicolas Cavallari <nicolas.cavallari@green-communications.fr>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pull SoC DT updates from Arnd Bergmann:
"About a quarter of the changes are for 32-bit arm, mostly filling in
device support for existing machines and adding minor cleanups, mostly
for Qualcomm and Samsung based machines.
Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from
Rockchips that have been around for a while but were lacking kernel
support so far: RV1126 is a Vision SoC with an NPU and is used in the
Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design
for TV boxes and so far only comes with a dts for its refernece
design.
The other 32-bit boards that were added are two ASpeed AST2600 based
BMC boards, the Microchip sam9x60_curiosity development board (Armv5
based!), the Enclustra PE1 FPGA-SoM baseboard, and a few more boards
for i.MX53 and i.MX6ULL.
On the RISC-V side, there are fewer patches, but a total of ten new
single-board computers based on variations of the Allwinner D1/T113
chip, plus one more board based on Microchip Polarfire.
As usual, arm64 has by far the most changes here, with over 700
non-merge changesets, among them over 400 alone for Qualcomm. The
newly added SoCs this time are all recent high-end embedded SoCs for
various markets, each on comes with support for its reference board:
- Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones
- Qualcomm QDU1000/QRU1000 5G RAN platform
- Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs
- TI J784S4 for industrial and automotive applications
In total, there are 46 new arm64 machines:
- Reference platforms for each of the five new SoCs
- Three Amlogic based development boards
- Six embedded machines based on NXP i.MX8MM and i.MX8MP
- The Mediatek mt7986a based Banana Pi R3 router
- Six tablets based on Qualcomm MSM8916 (Snapdragon 410), SM6115
(Snapdragon 662) and SM8250 (Snapdragon 865)
- Two LTE dongles, also based on MSM8916
- Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610),
SDM450 and SDM632
- Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c)
- Nine development boards based on Rockchips RK3588, RK3568, RK3566
and RK3328.
- Five development machines based on TI K3 (AM642/AM654/AM68/AM69)
The cleanup of dtc warnings continues across all platforms, adding to
the total number of changes"
* tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1035 commits)
dt-bindings: riscv: correct starfive visionfive 2 compatibles
ARM: dts: socfpga: Add enclustra PE1 devicetree
dt-bindings: altera: Add enclustra mercury PE1
arm64: dts: qcom: msm8996: align RPM G-Link clock-controller node with bindings
arm64: dts: qcom: qcs404: align RPM G-Link node with bindings
arm64: dts: qcom: ipq6018: align RPM G-Link node with bindings
arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobam
arm64: dts: qcom: sc7280: Adjust zombie PWM frequency
arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly
arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c busses
arm64: dts: qcom: sm7225-fairphone-fp4: move status property down
arm64: dts: qcom: pmk8350: Use the correct PON compatible
arm64: dts: qcom: sc8280xp-x13s: Enable external display
arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink
arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks
arm64: dts: qcom: sm8350-hdk: enable GPU
arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
arm64: dts: qcom: sm8350: finish reordering nodes
arm64: dts: qcom: sm8350: move more nodes to correct place
arm64: dts: qcom: sm8350: reorder device nodes
...
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Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The following build warnings are seen when running:
make dtbs_check DT_SCHEMA_FILES=fsl-imx-uart.yaml
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb: serial@30860000: cts-gpios: False schema does not allow [[33, 3, 1]]
From schema: Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb: serial@30860000: rts-gpios: False schema does not allow [[33, 5, 1]]
From schema: Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml
...
The imx8m Venice Gateworks boards do not expose the UART RTS and CTS
as native UART pins, so 'uart-has-rtscts' should not be used.
Using 'uart-has-rtscts' with 'rts-gpios' is an invalid combination
detected by serial.yaml.
Fix the problem by removing the incorrect 'uart-has-rtscts' property.
Fixes: 27c8f4ccc1b9 ("arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes")
Fixes: d9a9a7cf32c9 ("arm64: dts: imx8m{m,n}-venice-*: add missing uart-has-rtscts property to UARTs")
Fixes: 870f645b396b ("arm64: dts: imx8mp-venice-gw74xx: add WiFi/BT module support")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The GW7901 has USB2 routed to a USB VBUS supply with over-current
protection via an active-low pin. Define the OC pin polarity properly.
Fixes: 2b1649a83afc ("arm64: dts: imx: Add i.mx8mm Gateworks gw7901 dts support")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fix the following dtbs_check warning on all of i.MX8M variants:
"
opp-table: Unevaluated properties are not allowed ('opp-25M', 'opp-100M', 'opp-750M' were unexpected)
"
Using the following command:
"
$ sed -i '/opp-[0-9]\+M/ s@M {@000000 {@' arch/arm64/boot/dts/freescale/imx8m*
"
The Documentation/devicetree/bindings/opp/opp-v2-base.yaml expects the OPP
subnode names to be full frequency listings in Hz without unit suffixes.
Only the i.MX8M DTs are affected per "git grep 'opp-[0-9]\+M'", so fix them.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add I2C GPIO bus recovery support by adding scl-gpios and sda-gpios for the
various I2C busses on Gateworks Venice boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Since commit 65ac79e18120 ("net: dsa: microchip: add the phylink
get_caps") the phy-mode must be set otherwise the switch driver will
assume "NA" mode and invalidate the port.
Fixes: 65ac79e18120 ("net: dsa: microchip: add the phylink get_caps")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Remove the unnecessary cpu_alert0 and cpu_crit0 TMU node overrides as
these are added dynamically by boot firmware based on CPU temperature
grade.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Define the missing clock-names property for the pcie_phy required by
the fsl,imx8-pcie-phy dt bindings.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add the missing 'uart-has-rtscts' property to UART's that have hardware
flow control capability.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add gpio-line-names for the various GPIO's used on Gateworks Venice
boards. Note that these GPIO's are typically 'configured' in Boot
Firmware via gpio-hog therefore we only configure line names to keep the
boot firmware configuration from changing on kernel init.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Since commit b21269b12e48 ("arm64: dts: imx8mm: add GPC node") the
GW7901 will hang during kernel init because it does not power the unused
GPU voltage rails on the IMX8MM. Disable pgc_gpumix to work around this.
We also disable the GPU devices that depend on the gpumix power domain
and pgc_gpu to avoid them staying in a probe deferred state forever.
Additionally as the MIPI voltage rail is also not connected on this
board we disable pgc_mipi and disp_blk_ctrl.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Enable internal pull-down on UART transceiver GPIO config pins.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The USB hub has it's reset as GPIO4_IO17 but can be sub-loaded and
VBUS provided by a VBUS regulator with GPIO4_IO2 as the enable and
GPIO1_IO15 as the active-low over-current.
Enable pull-up for GPIO4_IO17 to keep hub out of reset and move VBUS
enable to GPIO4_IO2. Additionally enable pull-up on GPIO1_IO15 so that
if the hub is loaded it never over-currents.
This allows USB to work in both configurations without a device-tree
change.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The following dtc build warning is seen with W=1:
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts:291.14-397.4: Warning (avoid_unnecessary_addr_size): /soc@0/bus@30800000/i2c@30a20000/gsc@20: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Remove the unnecessary #address-cells/#size-cells to fix it.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
- i.MX8M Mini SoC
- LPDDR4 DRAM
- eMMC FLASH
- SPI FRAM
- Gateworks System Controller (GSC)
- Atmel ATECC Crypto Authentication
- USB 2.0
- Microchip GbE Switch
- Multiple multi-protocol RS232/RS485/RS422 Serial ports
- onboard 802.11ac WiFi / BT
- microSD socket
- miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets
- Wide range DC power input
- 802.3at PoE
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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