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The "media_ldb_root_clk" is the gate clock to enable or disable the clock
provided by CCM(Clock Control Module) to LDB instead of the "media_ldb"
clock which is the parent of the "media_ldb_root_clk" clock as a composite
clock. Fix LDB clocks property by referencing the "media_ldb_root_clk"
clock instead of the "media_ldb" clock.
Fixes: e7567840ecd3 ("arm64: dts: imx8mp: Reorder clock and reg properties")
Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pull SoC DT updates from Arnd Bergmann:
"There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
already supported chips.
The other six new SoCs are all part of existing arm64 families, but
are somewhat more interesting:
- Samsung ExynosAutov920 is an automotive chip, and the first one we
support based on the Cortex-A78AE core with lockstep mode.
- Google gs101 (Tensor G1) is the chip used in a number of Pixel
phones, and is grouped with Samsung Exynos here since it is based
on the same SoC design, sharing most of its IP blocks with that
series.
- MediaTek MT8188 is a new chip used for mid-range tablets and
Chromebooks, using two Cortex-A78 cores where the older MT8195 had
four of them.
- Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
phone SoC and the first supported chip based on Cortex-X4,
Cortex-A720 and Cortex-A520.
- Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop
chip using the custom Oryon cores.
- Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
Cortex-A76 and Cortex-A55
In terms of boards, we have
- Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.
- Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy
RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub
and a few Rockchips SBCs
- Some ComXpress boards based on Marvell CN913x, which is the
follow-up to Armada 7xxx/8xxx.
- Six new industrial/embedded boards based on NXP i.MX8 and i.MX9
- Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.
- Toradex Verdin AM62 Mallow carrier for TI AM62
- Huashan Pi board based on the SophGo CV1812H RISC-V chip
- Two boards based on Allwinner H616/H618
- A number of reference boards for various added SoCs from Qualcomm,
Mediatek, Google, Samsung, NXP and Spreadtrum
As usual, there are cleanups and warning fixes across all platforms as
well as added features for several of them"
* tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits)
ARM: dts: usr8200: Fix phy registers
arm64: dts: intel: minor whitespace cleanup around '='
arm64: dts: socfpga: agilex: drop redundant status
arm64: dts: socfpga: agilex: add unit address to soc node
arm64: dts: socfpga: agilex: move firmware out of soc node
arm64: dts: socfpga: agilex: move FPGA region out of soc node
arm64: dts: socfpga: agilex: align pin-controller name with bindings
arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
arm64: dts: socfpga: stratix10: add unit address to soc node
arm64: dts: socfpga: stratix10: move firmware out of soc node
arm64: dts: socfpga: stratix10: move FPGA region out of soc node
arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
ARM: dts: socfpga: align NAND controller name with bindings
ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
arm64: dts: rockchip: Fix led pinctrl of lubancat 1
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
...
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The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Even if the 'dsp' node is disabled the memory intended to be used by the
DSP is reserved. This limits the memory range suitable for CMA allocation.
Thus disable the dsp_reserved node. DSP users need to enable it in parallel
to the 'dsp' node.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The NPU is based on the Vivante GC8000 and its power-domain
is controlled my pgc_mlmix. Since the power-domain uses
some of these clocks, setup the clock parent and rates
inside the power-domain, and add the NPU node.
The data sheet states the CLK_ML_AHB should be 300MHz for
nominal, but 800MHz clock will divide down to 266 instead.
Boards which operate in over-drive mode should update the
clocks on their boards accordingly. When the driver loads,
the NPU numerates as:
etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The i.MX8MP and i.MX8MQ devices both use the same DWC3 controller and
are both affected by a known issue with the controller due to specific
behaviour when park mode is enabled in SuperSpeed host mode operation.
Under heavy USB traffic from multiple endpoints the controller will
sometimes incorrectly process transactions such that some transactions
are lost, or the controller may hang when processing transactions. When
the controller hangs it does not recover.
This issue is documented partially within the linux-imx vendor kernel
which references a Synopsys STAR number 9001415732 in commits [1] and
additional details in [2]. Those commits provide some additional
controller internal implementation specifics around the incorrect
behaviour of the SuperSpeed host controller operation when park mode is
enabled.
The summary of this issue is that the host controller can incorrectly
enter/exit park mode such that part of the controller is in a state
which behaves as if in park mode even though it is not. In this state
the controller incorrectly calculates the number of TRBs available which
results in incorrect access of the internal caches causing the overwrite
of pending requests in the cache which should have been processed but
are ignored. This can cause the controller to drop the requests or hang
waiting for the pending state of the dropped requests.
The workaround for this issue is to disable park mode for SuperSpeed
operation of the controller through the GUCTL1[17] bit. This is already
available as a quirk for the DWC3 controller and can be enabled via the
'snps,parkmode-disable-ss-quirk' device tree property.
It is possible to replicate this failure on an i.MX8MP EVK with a USB
Hub connecting 4 SuperSpeed USB flash drives. Performing continuous
small read operations (dd if=/dev/sd... of=/dev/null bs=16) on the block
devices will result in device errors initially and will eventually
result in the controller hanging.
[13240.896936] xhci-hcd xhci-hcd.0.auto: WARN Event TRB for slot 4 ep 2 with no TDs queued?
[13240.990708] usb 2-1.3: reset SuperSpeed USB device number 5 using xhci-hcd
[13241.015582] sd 2:0:0:0: [sdc] tag#0 UNKNOWN(0x2003) Result: hostbyte=0x07 driverbyte=DRIVER_OK cmd_age=0s
[13241.025198] sd 2:0:0:0: [sdc] tag#0 CDB: opcode=0x28 28 00 00 00 03 e0 00 01 00 00
[13241.032949] I/O error, dev sdc, sector 992 op 0x0:(READ) flags 0x80700 phys_seg 25 prio class 2
[13272.150710] usb 2-1.2: reset SuperSpeed USB device number 4 using xhci-hcd
[13272.175469] sd 1:0:0:0: [sdb] tag#0 UNKNOWN(0x2003) Result: hostbyte=0x03 driverbyte=DRIVER_OK cmd_age=31s
[13272.185365] sd 1:0:0:0: [sdb] tag#0 CDB: opcode=0x28 28 00 00 00 03 e0 00 01 00 00
[13272.193385] I/O error, dev sdb, sector 992 op 0x0:(READ) flags 0x80700 phys_seg 18 prio class 2
[13434.846556] xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command
[13434.854592] xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead
[13434.862553] xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
[1] https://github.com/nxp-imx/linux-imx/commit/97a5349d936b08cf301730b59e4e8855283f815c
[2] https://github.com/nxp-imx/linux-imx/commit/b4b5cbc5a12d7c3b920d1d7cba0ada3379e4e42b
Fixes: fb8587a2c165 ("arm64: dtsi: imx8mp: add usb nodes")
Fixes: ad37549cb5dc ("arm64: dts: imx8mq: add USB nodes")
Signed-off-by: Nathan Rossi <nathan.rossi@digi.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add both CCM interrupts as mentioned in RM.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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i.MX fixes for 6.6:
- A couple of i.MX8MP device tree changes from Adam Ford to fix clock
configuration regressions caused by 16c984524862 ("arm64: dts: imx8mp:
don't initialize audio clocks from CCM node").
- Fix pmic-irq-hog GPIO line in imx93-tqma9352 device tree.
- Fix a mmemory leak with error handling path of imx_dsp_setup_channels()
in imx-dsp driver.
- Fix HDMI node in imx8mm-evk device tree.
- Add missing clock enable functionality for imx8mm_soc_uid() function
in soc-imx8m driver.
- Add missing imx8mm-prt8mm.dtb build target.
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The 'funnel' node does not contain a register range, so it should
be placed outside of the soc node to fix schema warnings from
simple-bus.yaml.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The i.MX8MP has a micfil controller which is used for interfacing
with a pulse density microphone. Add the node and mark it as
disabled by default.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The i.MX8MP has an asynchronous sample rate converter which seems
to be the same as what is available on the i.MX8M Nano.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Commit 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks
from CCM node") removed the Audio clocks from the main clock node, because
the intent is to force people to setup the audio PLL clocks per board
instead of having a common set of rates, since not all boards may use
the various audio PLL clocks in the same way.
Unfortunately, with this parenting removed, the SDMA2 and SDMA3
clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
and that clock is enabled by pgc_audio.
Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
AHB, always 1:1 mode, to make sure there is enough throughput for all
the audio use cases."
Instead of cluttering the clock node, place the clock rate and parent
information into the pgc_audio node.
With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB,
and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
400MHz again.
Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The reg size of etm nodes is incorrectly set to 64k instead of 4k. This
leads to a crash when calling amba_read_periphid(). After corrected reg
size, amba_read_periphid() retrieve the correct periphid.
arm,primecell-periphid were removed from the etm nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
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The audio clocks should be intitialized to the correct rate by the subsystem
using them. There is no need to always initialize them from the CCM node
assigned-clocks property. This way boards using the audio clocks in a non-
standard way can change them without first duplicating the CCM clock
setup.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add coresight trace components (ETM, ETF, ETB and Funnel).
┌───────┐ ┌───────┐ ┌───────┐
│ CPU0 ├─►│ ETM0 ├─►│ │
└───────┘ └───────┘ │ │
│ │
┌───────┐ ┌───────┐ │ ATP │
│ CPU1 ├─►│ ETM1 ├─►│ │
└───────┘ └───────┘ │ │
│ FUNNEL│
┌───────┐ ┌───────┐ │ │
│ CPU2 ├─►│ ETM2 ├─►│ │
└───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐
│ │ │ │ │ │
┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │
│ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │
└───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI
│ │ │ ▲
▼ ▼ ▼ │
┌───────────────────────────┐ ┌─────┐ ┌─┴──┐
│ ATP FUNNEL ├──►│ETF ├─► │ETR │
└───────────────────────────┘ └─────┘ └────┘
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add DT node for the DeWarp Engine of the i.MX8MP.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Sort AIPS4 nodes by node unit-address . No functional change .
Suggested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The base address of NOC is bigger than aips5, but smaller than aips4.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There are a few clocks whose parents are set in mipi_dsi
and lcdif nodes, but these clocks are used by the media_blk_ctrl
power domain. This may cause an issue when re-parenting, because
the media_blk_ctrl may start the clocks before the reparent is
done resulting in a disp_pixel clock having the wrong parent and
rate.
Fix this by moving the assigned-clock-parents and rates to the
media_blk_ctrl node to configure these clocks before they are enabled.
After this patch, both disp1_pix_root and dixp2_pix_root clock
become children of the video_pll1.
video_pll1_ref_sel 24000000
video_pll1 1039500000
video_pll1_bypass 1039500000
video_pll1_out 1039500000
media_disp2_pix 1039500000
media_disp2_pix_root_clk 1039500000
media_disp1_pix 1039500000
media_disp1_pix_root_clk 1039500000
Fixes: eda09fe149df ("arm64: dts: imx8mp: Add display pipeline components")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
needed to get audio operational on i.MX8MP .
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add a DT node for the i.MX8MP ISI instance, and model to connection to
two CSI-2 receivers (CSIS).
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add DT nodes for the two CSI-2 receivers of the i.MX8MP.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pull ARM SoC devicetree updates from Arnd Bergmann:
"The devicetree changes overall are again dominated by the Qualcomm
Snapdragon platform that weighs in at over 300 changesets, but there
are many updates across other platforms as well, notably Mediatek,
NXP, Rockchips, Renesas, TI, Samsung and ST Microelectronics. These
all add new features for existing machines, as well as new machines
and SoCs.
The newly added SoCs are:
- Allwinner T113-s, an Cortex-A7 based variant of the RISC-V based D1
chip.
- StarFive JH7110, a RISC-V SoC based on the Sifive U74 core like its
JH7100 predecessor, but with additional CPU cores and a GPU.
- Apple M2 as used in current Macbook Air/Pro and Mac Mini gets
added, with comparable support as its M1 predecessor.
- Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC
- Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs, based on
the Cortex-A53 and Cortex-A73 cores, respectively.
- Qualcomm sa8775p is an automotive SoC derived from the Snapdragon
family.
Including the initial board support for the added SoC platforms, there
are 52 new machines. The largest group are 19 boards industrial
embedded boards based on the NXP i.MX6 (32-bit) and i.MX8 (64-bit)
families.
Others include:
- Two boards based on the Allwinner f1c200s ultra-low-cost chip
- Three 'Banana Pi' variants based on the Amlogic g12b (A311D, S922X)
SoC.
- The Gl.Inet mv1000 router based on Marvell Armada 3720
- A Wifi/LTE Dongle based on Qualcomm msm8916
- Two robotics boards based on Qualcomm QRB chips
- Three Snapdragon based phones made by Xiaomi
- Five developments boards based on various Rockchip SoCs, including
the rk3588s-khadas-edge2 and a few NanoPi models
- The AM625 Beagleplay industrial SBC
Another 14 machines get removed: both boards for the obsolete 'oxnas'
platform, three boards for the Renesas r8a77950 SoC that were only for
pre-production chips, and various chromebook models based on the
Qualcomm Sc7180 'trogdor' design that were never part of products"
* tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (836 commits)
arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro
arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b
arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B
arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b
arm64: dts: apple: t8112: Add PWM controller
arm64: dts: apple: t600x: Add PWM controller
arm64: dts: apple: t8103: Add PWM controller
arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x
ARM: dts: nomadik: Replace deprecated spi-gpio properties
ARM: dts: aspeed-g6: Add UDMA node
ARM: dts: aspeed: greatlakes: add mctp device
ARM: dts: aspeed: greatlakes: Add gpio names
ARM: dts: aspeed: p10bmc: Change power supply info
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
arm64: dts: mediatek: mt6795: Add tertiary PWM node
arm64: dts: rockchip: add panel to Anbernic RG353 series
dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC
dt-bindings: arm: fsl: Add chargebyte Tarragon
dt-bindings: vendor-prefixes: add chargebyte
...
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Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus.
This makes the DSI display pipeline available on this SoC.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The i.MX8MP includes the same GPT blocks as the i.MX6DL. Add all 6
instances.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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0x238 is the offset for PANIC0_THRES, so the length needs to be greater
than that. Use the size from memory map from reference manual.
Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The 'axi' clock are the bus APB clock, the 'disp_axi' clock are the
pixel data AXI clock. The naming is confusing. Fix the clock order.
Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Align the clock and reg properties order with example bindings
and the rest of the imx8mp.dtsi . No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This block should not be compatible with simple-bus and misuse it that way.
Instead, the driver should scan its subnodes and bind drivers to them.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add i.MX8MP PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Pull SoC DT updates from Arnd Bergmann:
"About a quarter of the changes are for 32-bit arm, mostly filling in
device support for existing machines and adding minor cleanups, mostly
for Qualcomm and Samsung based machines.
Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from
Rockchips that have been around for a while but were lacking kernel
support so far: RV1126 is a Vision SoC with an NPU and is used in the
Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design
for TV boxes and so far only comes with a dts for its refernece
design.
The other 32-bit boards that were added are two ASpeed AST2600 based
BMC boards, the Microchip sam9x60_curiosity development board (Armv5
based!), the Enclustra PE1 FPGA-SoM baseboard, and a few more boards
for i.MX53 and i.MX6ULL.
On the RISC-V side, there are fewer patches, but a total of ten new
single-board computers based on variations of the Allwinner D1/T113
chip, plus one more board based on Microchip Polarfire.
As usual, arm64 has by far the most changes here, with over 700
non-merge changesets, among them over 400 alone for Qualcomm. The
newly added SoCs this time are all recent high-end embedded SoCs for
various markets, each on comes with support for its reference board:
- Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones
- Qualcomm QDU1000/QRU1000 5G RAN platform
- Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs
- TI J784S4 for industrial and automotive applications
In total, there are 46 new arm64 machines:
- Reference platforms for each of the five new SoCs
- Three Amlogic based development boards
- Six embedded machines based on NXP i.MX8MM and i.MX8MP
- The Mediatek mt7986a based Banana Pi R3 router
- Six tablets based on Qualcomm MSM8916 (Snapdragon 410), SM6115
(Snapdragon 662) and SM8250 (Snapdragon 865)
- Two LTE dongles, also based on MSM8916
- Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610),
SDM450 and SDM632
- Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c)
- Nine development boards based on Rockchips RK3588, RK3568, RK3566
and RK3328.
- Five development machines based on TI K3 (AM642/AM654/AM68/AM69)
The cleanup of dtc warnings continues across all platforms, adding to
the total number of changes"
* tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1035 commits)
dt-bindings: riscv: correct starfive visionfive 2 compatibles
ARM: dts: socfpga: Add enclustra PE1 devicetree
dt-bindings: altera: Add enclustra mercury PE1
arm64: dts: qcom: msm8996: align RPM G-Link clock-controller node with bindings
arm64: dts: qcom: qcs404: align RPM G-Link node with bindings
arm64: dts: qcom: ipq6018: align RPM G-Link node with bindings
arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobam
arm64: dts: qcom: sc7280: Adjust zombie PWM frequency
arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly
arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c busses
arm64: dts: qcom: sm7225-fairphone-fp4: move status property down
arm64: dts: qcom: pmk8350: Use the correct PON compatible
arm64: dts: qcom: sc8280xp-x13s: Enable external display
arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink
arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks
arm64: dts: qcom: sm8350-hdk: enable GPU
arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
arm64: dts: qcom: sm8350: finish reordering nodes
arm64: dts: qcom: sm8350: move more nodes to correct place
arm64: dts: qcom: sm8350: reorder device nodes
...
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Reorder the PCIe clock in DT to match YAML DT schema. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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LCDIF2 is directly attached to the LVDS Display Bridge (LDB).
Both need the same clock source (VIDEO_PLL1).
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Richard Leitner <richard.leitner@linux.dev>
Tested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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It is preferred to use syscon per bindind doc
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add DT nodes for the Hantro VPU found in i.MX8MP SoC.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There is an SPBA bus on AIPS3 which includes ecspi1-3,
UART1-3, and Flexcan1-2 according to the TRM.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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dt_binding_check detects an issue with the pgc_hsiomix power
domain:
pgc: 'power-domains@17' does not match any of the regexes
This is because 'power-domains' should be 'power-domain'
Fixes: 2ae42e0c0b67 ("arm64: dts: imx8mp: add HSIO power-domains")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The GPC node references an interrupt parent, but it doesn't
state the interrupt itself. According to the TRM, this IRQ
is 87. This also eliminate an error detected from dt_binding_check
Fixes: fc0f05124621 ("arm64: dts: imx8mp: add GPC node with GPU power domains")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The HSIO blk-ctrl exposes the high performance PLL as
a simple clock.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Lukas F. Hartmann <lukas@mntre.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The only difference in PCIe clock configuration between boards is how
the PCIe reference clock is generated. The refclock configuration is
fully contained in the PCIe PHY node, so the PCIe controller clocks
can be set up in the SoC dtsi, as there is no reason for any board to
use a different configuration.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Align the SoC unique ID DT node unit address with its reg property.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fixes: cbff23797fa1 ("arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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After commit cf7f3f4fa9e5 ("clk: imx8mp: fix usb_root_clk parent"),
usb_root_clk is no longer for suspend clock so update dts accordingly
to use right bus clock and suspend clock.
Fixes: fb8587a2c165 ("arm64: dtsi: imx8mp: add usb nodes")
Cc: stable@vger.kernel.org # ed1f4ccfe947: clk: imx: imx8mp: add shared clk gate for usb suspend clk
Cc: stable@vger.kernel.org # v5.19+
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add mlmix power domain
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fix the following dtbs_check warning on all of i.MX8M variants:
"
opp-table: Unevaluated properties are not allowed ('opp-25M', 'opp-100M', 'opp-750M' were unexpected)
"
Using the following command:
"
$ sed -i '/opp-[0-9]\+M/ s@M {@000000 {@' arch/arm64/boot/dts/freescale/imx8m*
"
The Documentation/devicetree/bindings/opp/opp-v2-base.yaml expects the OPP
subnode names to be full frequency listings in Hz without unit suffixes.
Only the i.MX8M DTs are affected per "git grep 'opp-[0-9]\+M'", so fix them.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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i.MX8MP ECSPI is derived from i.MX6UL, so update compatible
Add assigned-clocks settings
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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