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2023-05-13arm64: dts: s32: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: s32g274a-evb.dtb: l2-cache1: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20230421223202.115472-1-krzysztof.kozlowski@linaro.org
2022-11-15arm64: dts: Update cache properties for freescalePierre Gondois
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Chester Lin <clin@suse.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-13arm64: dts: freescale: s32v234: use generic name busPeng Fan
Per devicetree specification, generic names are recommended to be used, such as bus. AIPS is a AHB - IP bridge bus, so we could use bus as node name. Script: sed -i "s/\<aips@/bus@/" arch/arm64/boot/dts/freescale/*.dtsi sed -i "s/\<aips-bus@/bus@/" arch/arm64/boot/freescale/*.dtsi Cc: Phu Luu An <phu.luuan@nxp.com> Cc: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Cc: Mihaela Martinas <Mihaela.Martinas@freescale.com> Cc: Dan Nica <dan.nica@nxp.com> Cc: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: fsl: Add device tree for S32V234-EVBStoica Cosmin-Stefan
Add initial version of device tree for S32V234-EVB, including nodes for the 4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and Generic Interrupt Controller (GIC). Keep SoC level separate from board level to let future boards with this SoC share common properties, while the dts files will keep board-dependent properties. Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com> Signed-off-by: Phu Luu An <phu.luuan@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>