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2023-06-09Merge tag 'hisi-arm64-dt-for-6.5' of https://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into soc/dt ARM64: DT: HiSilicon ARM64 DT updates for v6.5 - Clean up the pinctrl-single node names and correct the #size-cells of the pinctrl controller nodes * tag 'hisi-arm64-dt-for-6.5' of https://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Unify pinctrl-single pin group nodes Link: https://lore.kernel.org/r/6482C916.1010507@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-07arm64: dts: hisilicon: Unify pinctrl-single pin group nodesTony Lindgren
We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it. Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-05-16arm64: dts: hisilicon: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-27arm64: dts: hisilicon: align UART node name with bindingsKrzysztof Kozlowski
Bindings expect UART/serial node names to be "serial". Link: https://lore.kernel.org/r/20230123151516.369130-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13arm64: dts: hisilicon: align LED node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern: hisilicon/hi3660-hikey960.dtb: leds: wlan_active_led: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) Link: https://lore.kernel.org/r/20221125144140.477225-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-15arm64: dts: Update cache properties for hisiliconPierre Gondois
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2022-06-20arm64: dts: hisilicon: correct gpio-keys propertiesKrzysztof Kozlowski
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-10-krzysztof.kozlowski@linaro.org
2022-06-20arm64: dts: hisilicon: align gpio-key node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-9-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: hisilicon: adjust whitespace around '='Krzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204453.832681-1-krzysztof.kozlowski@linaro.org
2022-04-19arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFSKrzysztof Kozlowski
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
2021-09-22arm64: dts: hisilicon: align operating-points table name with dtschemaKrzysztof Kozlowski
Align the name of operating-points node to dtschema to fix warnings like: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-09-18arm64: dts: hisilicon: fix arm,sp805 compatible stringMichael Walle
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell"; The current compatible string doesn't exist at all. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-09-18arm64: dts: hisilicon: Add support for Hikey 970 PMICMauro Carvalho Chehab
Add a device tree for the HiSilicon 6421v600 SPMI PMIC, used on HiKey970 board. As we now have support for it, change the fixed regulators used by the SD I/O to use the proper LDO supplies. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-08-13arm64: dts: HiSilicon: hi3660: address a PCI warningMauro Carvalho Chehab
When the driver is registered, it produces a warning when registering the PCI bridge: [ 5.363450] pci_bus 0000:00: root bus resource [bus 00-01] [ 5.396998] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-01] (conflicts with (null) [bus 00-01]) [ 5.284831] pci 0000:00:00.0: PCI bridge to [bus 01-ff] The reason is that the bus-range is wrong. Address it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-06-17arm64: dts: hisilicon: use the correct HiSilicon copyrightHao Fang
s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en. Signed-off-by: Hao Fang <fanghao11@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hi3670.dtsi: add I2C settingsMauro Carvalho Chehab
The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hikey970-pinctrl.dtsi: add missing pinctrl settingsMauro Carvalho Chehab
There are several pinctrl settings that are missing at this DT file. Also, the entries are out of order. Add the missing bits, as they'll be required by the DRM driver - and probably by other drivers not upstreamed yet. Reorder the entres, adding the missing bits. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hi3670.dtsi: add iomcu_rstMauro Carvalho Chehab
This is required in order to support USB. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: delete unused property smmu-cb-memtypeZhen Lei
The "smmu-cb-memtype" is a private property developed by the Hisilicon driver in the early stage and is not used now. So delete it. Otherwise, below YAML check warnings are reported: arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml: iommu@a0040000: \ 'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/hisilicon/hip07-d05.dt.yaml: iommu@a0040000: \ 'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: avoid irrelevant nodes being mistakenly identified as ↵Zhen Lei
PHY nodes Currently, the names of several nodes incorrectly match common PHY provider schema. And the phy-provider.yaml requires them must have property "#phy-cells". As a result, false positives similar to the following are reported: usb2-phy@120: '#phy-cells' is a required property Change their names slightly so that they do not match pattern: "^(|usb-|usb2-|usb3-|pci-|pcie-|sata-)phy(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: normalize the node name of the localbusZhen Lei
Change the node name of the localbus to match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'. This error is detected by simple-bus.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: normalize the node name of the module thermalZhen Lei
1. Change the node name of the thermal zone to match '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', add suffix "-thermal". 2. Change the node name of the trip point to match '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', delete character "@". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: place clock-names "bus" before "core"Zhen Lei
Look at the clock-names schema defined in arm,mali-utgard.yaml: clock-names: items: - const: bus - const: core The "bus" needs to be placed before the "core". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: separate each group of data in the property "ranges"Zhen Lei
Do not write the "ranges" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported: soc: pcie@a0090000:ranges: [[33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536]] is not valid under \ any of the given schemas (Possible causes of the failure): soc: pcie@a0090000:ranges: [[33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536]] is not of type 'boolean' soc: pcie@a0090000:ranges:0: [33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"Jisheng Zhang
This is to remove similar errors as below: OF: /.../gpio-port@0: could not find phandle Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support") explained the reason of above errors well and added the generic "ngpios" property, let's use it. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hi3660: Harmonize DWC USB3 DT nodes nameSerge Semin
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yamlZhen Lei
The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by pl011.yamlZhen Lei
The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by spi-pl022.yamlZhen Lei
The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the UART devicesZhen Lei
Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the usb devicesZhen Lei
Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the SMMU devicesZhen Lei
Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: place clock-names "biu" before "ciu"Zhen Lei
Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: remove unused property pinctrl-namesZhen Lei
uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names" can be deleted. In fact, the property "pinctrl-names" depends on the property "pinctrl-0". So the errors similar to the following will be reported by pinctrl-consumer.yaml. serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: write the values of property-units into a uint32 arrayZhen Lei
Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml. ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: separate each group of data in the property "reg"Zhen Lei
Do not write the "reg" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \ 6291456] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the ITS devicesZhen Lei
Change the node name of the ITS devices to match "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although "interrupt-controller" is allowed, but "msi-controller" is preferred. Otherwise, "interrupt-controller@b7000000: False schema does not allow" will be reported by arm,gic-v3.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-09-14arm64: dts: hisilicon: Fix SP805 clocksAndre Przywara
The SP805 DT binding requires two clocks to be specified, but Hisilicon platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-09-14arm64: dts: hisilicon: replace status value "ok" by "okay"Adrian Schmutzler
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-07-17arm64: dts: hisilicon: hikey: fixes to comply with adi, adv7533 DT bindingRicardo Cañuelo
hi3660-hikey960.dts: Define a 'ports' node for 'adv7533: adv7533@39' and the 'adi,dsi-lanes' property to make it compliant with the adi,adv7533 DT binding. This fills the requirements to meet the binding requirements, remote endpoints are not defined. hi6220-hikey.dts: Change property name s/pd-gpio/pd-gpios, gpio properties should be plural. This is just a cosmetic change. Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-07-17dts: hi3660: Add support for basic usb gadget on Hikey960John Stultz
This patch adds basic core dwc3, usb phy and rt1711h nodes for usb support on Hikey960. This does not enable the mux/hub functionality on the board, so the USB-A host ports will not function, but does allow the USB-C port to function in gadget mode (unfortunately not in host, as the hub/mux functionality is needed to enable vbus output to power devices in host mode). This is based on an old patch originally by Yu Chen. Cc: Yu Chen <chenyu56@huawei.com> Cc: Chunfeng Yun <chunfeng.yun@mediatek.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: YongQin Liu <yongqin.liu@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-07-17arm64: dts: hisilicon: Align UART nodename with dtschemaKrzysztof Kozlowski
Fix dtschema validator warnings like: uart@f8015000: $nodename:0: 'uart@f8015000' does not match '^serial(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-07-17arm64: dts: hisilicon: Use phandles for overriding nodes in hi6220Krzysztof Kozlowski
When overriding nodes, usage of phandles instead of full paths reduces possible mistakes (e.g. in duplicated unit address) and removes duplicate data. The UART nodes were extended via full path and phandle which makes it difficult to review and spot actual differences. No functional change (no difference in dtx_diff). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-05-07arm64: dts: hi6220: Add CTI optionsMike Leach
Adds in CTI device tree information for the Hikey620 board. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-05-07arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconfLoic Poulain
Only the pinmux was selected, not the pinconf, leading to spi issues. Increase drive strength so that max speed (25Mhz) can be achieved. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-01-08arm64: dts: hi3798cv200: correct PCIe 'bus-range' settingShawn Guo
The PCIe 'bus-range' setting is incorrect and causing the following message during boot. pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f]) Correct it to get rid of the message. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-01-06arm64: dts: hi3798cv200-poplar: add linux,rc-map-name for IRShawn Guo
It adds remote control map name for IR device, so that key event can be reported. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-10-26arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entryPeter Griffin
hi6220 has a Mali450 MP4 so lets add it into the DT. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-25Merge tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson
into arm/dt ARM64: DT: Hisilicon SoCs DT updates for v5.3 * Hi3660 SoC and related boards: - Added CoreSight trace components * Hi6220 SoC and related boards: - Updated CoreSight funnel and replicator using new bindings to fix warning * tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi3660: Add CoreSight support arm64: dts: hi6220: Update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: dts: hi3660: Add CoreSight supportWanglai Shi
This patch adds DT bindings for the CoreSight trace components on hi3660, which is used by 96boards Hikey960. Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com> Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
generated by cgit (git 2.34.1) at 2025-06-03 04:28:29 +0000