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2018-07-31Merge tag 'mvebu-dt64-4.19-2' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson
next/dt mvebu dt64 for 4.19 (part 2) Use more specific compatible for the Inside Secure SafeXcel on the Armada 37xx and the Armada 7K/8K SoCs. * tag 'mvebu-dt64-4.19-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-37xx: update the crypto engine compatible arm64: dts: marvell: armada-cp110: update the crypto engine compatible Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-14Merge tag 'mvebu-dt64-4.19-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson
next/dt mvebu dt64 for 4.19 (part 1) Armada 3700 - Add default memory reservation for ATF - Add a node for AVS support Fix eth3 connector name on the Macchiatobin * tag 'mvebu-dt64-4.19-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-37xx: reserve memory for ATF arm64: dts: marvell: armada-37xx: add the node allowing AVS support arm64: dts: marvell: mcbin: fix eth3 connector name Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-13arm64: dts: marvell: armada-37xx: update the crypto engine compatibleAntoine Tenart
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell Armada 37xx device tree accordingly. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-07-13arm64: dts: marvell: armada-cp110: update the crypto engine compatibleAntoine Tenart
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell cp110 device tree accordingly. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-29arm64: dts: marvell: armada-37xx: reserve memory for ATFVictor Gu
The PSCI area should be reserved in Linux for PSCI operations such as suspend/resume. Reserve 2MiB of memory which matches the area used by ATF (BL1, BL2, BL3x, see [1] in ATF source code). This covers all PSCI code and data area and is 2MiB aligned, which is required by Linux for huge pages handling. Please note that this is a default setup allowing to perform PSCI operations with legacy bootloaders. Recent bootloaders should update the region size/position accordingly. [1] plat/marvell/a3700/common/include/platform_def.h Signed-off-by: Victor Gu <xigu@marvell.com> [miquel.raynal@bootlin.com: reword of commit message, comment in the DTSI] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-29arm64: dts: marvell: armada-37xx: add the node allowing AVS supportGregory CLEMENT
In order to be able to use Adaptive Voltage Scaling, we need to add a reference to these registers. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-27arm64: dts: marvell: mcbin: fix eth3 connector nameBaruch Siach
The right most SFP connector on the Macchiatobin board and schematics is marked as CON13/CON14. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-23Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson
mvebu fixes for 4.17 (part 2) - Use correct size for ICU nodes (irq controller) on Armada 7K/8K - Fix "#cooling-cells" property's name on Synology DS116 (Armada 385) * tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu: arm: dts: armada: Fix "#cooling-cells" property's name arm64: dts: marvell: fix CP110 ICU node size Signed-off-by: Olof Johansson <olof@lixom.net>
2018-06-11Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Olof Johansson: "As always, a large number of DT updates. Too many to enumerate them all, but at a glance: New SoCs introduced in this release: - Amlogic: + Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set top boxes and other products. - Mediatek: + MT7623A, which is a flavor of the MT7623 family with other on-chip ethernet options. - Qualcomm: + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845 (Cortex-A75/A55 derivative) SoC that's one of the current high-end mobile SoCs. It's great to see mainline support for it. So far, you can't do much with it, since a lot of peripherals are not yet in the DTs but driver support for USB, GPU and other pieces are starting to trickle in. This might end up being a well-supported SoC upstream if the momentum keeps up. - Renesas: + R8A77990, a.k.a R-Car E3, a new automotive entertainment-targeted SoC. Currently only one Cortex-A53 CPU is enabled, we are eagerly awaiting more. So far, basic drivers such as serial, gpios, PMU and ethernet are enabled. + R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR GPU. Same here, basic set of drivers such as serial, gpios and ethernet enabled, and SMP support is also forthcoming. - STMicroelectronics: + STM32F469, very similar tih STM32F429 but with display support Enhancements to SoCs/platforms (DTS contents, some driver portions might not be in yet): - Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc - Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets - Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces - Marvell Berlin2CD: SMP support, thermal sensors - Mediatek MT7623: Highspeed DMA, audio support - Qualcomm IPQ8074 PCIe support, MSM8996 UFS support - Renesas: Watchdog and PMU support across many platforms - Rockchip RK3399: USB3 OTG support - Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3 - STMicro STM32: Lots of peripherals added to STM32MP175C - Uniphier: Ethernet support New boards: - Allwinner A20: Olimex A20-SOM-EVB-eMMC variant - Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version) - Allwinner A33: Nintendo NES/SuperNES Classic Edition - Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune - Berlin2CD: Valve Steam Link - Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1 - Broadcom: Raspberry Pi 3 B+ - Mediatek MT7623N and MT7623A: reference boards - Meson 8M2: Tronsmart MXIII Plus - NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj - Qualcomm MSM8974: Sony Xperia Z1 Compact support - Qualcomm SDM845: MTP development board - Renesas: Ebisu R8A77990 board - Renesas RZ/G1C: iwg23s: iWave G235-SDB - TI am335x: Pocketbeagle support" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits) ARM: dts: aspeed: Fix hwrng register address arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog arm64: dts: sprd: Add GPIO and GPIO keys device nodes arm64: dts: sprd: fix typo in 'remote-endpoint' arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator arm64: dts: fix regulator property name for wlan pcie endpoint arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS ARM: dts: pxa3xx: fix MMC clocks ARM: pxa: dts: add pin definitions for extended GPIOs ARM: pxa: dts: add gpio-ranges to gpio controller ARM: dts: ipq8074: Enable few peripherals for hk01 board ARM: dts: ipq8074: Add pcie nodes ARM: dts: ipq8074: Add peripheral nodes ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi ARM: dts: ipq4019: Change the max opp frequency ...
2018-05-25Merge tag 'berlin64-dt-for-v4.18' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dt Berlin64 DT changes for v4.18 * tag 'berlin64-dt-for-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin: arm64: dts: move berlin SoC files from marvell dir to synaptics dir arm64: dts: berlin4ct-*.dts: use SPDX-License-Identifier arm64: dts: berlin4ct: use SPDX-License-Identifier Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-24arm64: dts: move berlin SoC files from marvell dir to synaptics dirJisheng Zhang
Move device tree files as part of transition from Marvell berlin to Synaptics berlin. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
2018-05-24arm64: dts: berlin4ct-*.dts: use SPDX-License-IdentifierJisheng Zhang
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
2018-05-24arm64: dts: berlin4ct: use SPDX-License-IdentifierJisheng Zhang
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
2018-05-23arm64: dts: marvell: fix CP110 ICU node sizeMiquel Raynal
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the specification). Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-18arm64: dts: marvell: armada-37xx: mark the gpio controllers as irq controllerUwe Kleine-König
This allows to reference these gpio controller as interrupt parent. Also add a comment which cpu line names are managed by the controllers because "nb" and "sb" usually doesn't appear in schematics, but MPPX_Y do. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-17arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-linkAntoine Tenart
This patch adds a fixed-link node to the 10G interface of the 7040-db board. This is required as the mvpp2 driver now uses phylink. The best solution would have been to describe the SFP cage but they are not wired correctly, and thus unusable, so we chose to use fixed-link instead. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-17arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-linkAntoine Tenart
This patch adds a fixed-link node to both 10G interfaces of the 8040-db board. This is required as the mvpp2 driver now uses phylink. The best solution would have been to describe the SFP cages but they are not wired correctly, and thus unusable, so we chose to use fixed-link instead. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-17arm64: dts: marvell: mcbin: enable the fourth network interfaceAntoine Tenart
This patch enables the fourth network interface on the Marvell Macchiatobin. It is configured in the 2500Base-X PHY mode. The SFP cage is also described. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-17arm64: dts: marvell: mcbin: add 10G SFP supportRussell King
This patch adds the SFP cage description in the Marvell Armada 8040 mcbin, for both 10G interfaces. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> [Antoine: small reworks, commit message] Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-04-27ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet nodeMaxime Chevallier
Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk" clock to avoid system hangs when powering some network interfaces up. This issue appeared after a recent clock rework on Armada 7K/8K platforms. This commit adds the new clock and updates the documentation accordingly. [gregory.clement: use the real first commit to fix and add the cc:stable flag] Fixes: e3af9f7c6ece ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node") Cc: <stable@vger.kernel.org> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-04-27ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio nodeMaxime Chevallier
The Marvell XSMI controller needs 3 clocks to operate correctly : - The MG clock (clk 5) - The MG Core clock (clk 6) - The GOP clock (clk 18) This commit adds them, to avoid system hangs when using these interfaces. [gregory.clement: use the real first commit to fix and add the cc:stable flag] Fixes: f66b2aff46ea ("arm64: dts: marvell: add xmdio nodes for 7k/8k") Cc: <stable@vger.kernel.org> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-04-27arm64: dts: marvell: mark CP110 ahci as dma-coherentMark Kettenis
The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-04-27arm64: dts: armada-3720-espressobin: wire up spi flashEllie Reeves
This is the storage the machine boots from by default. The partitioning is taken from the U-Boot that is shipped with the board. There is some more space on the flash that isn't used. Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Ellie Reeves <ellierevves@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19arm64: dts: armada-3720-espressobin: Document URL for schematicUwe Kleine-König
The schematic of the espressobin is publicly available, add a comment where to find it. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodesGregory CLEMENT
This extra clock is needed to access the registers of the PCIe host controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "PCI: armada8k: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND nodeGregory CLEMENT
This extra clock is needed to access the registers of the NAND controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "mtd: nand: marvell: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto nodeGregory CLEMENT
This extra clock is needed to access the registers of the safexcel EIP97 used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "crypto: inside-secure - fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for the trng nodeGregory CLEMENT
This extra clock is needed to access the registers of the harware RNG used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "hwrng: omap - Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodesGregory CLEMENT
This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-19ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodesGregory CLEMENT
This extra clock is needed to access the registers of the USB host controller used on Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "usb: host: xhci-plat: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-09ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodesGregory CLEMENT
This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-27arm64: dts: marvell: use reworked NAND controller driver on Armada 8KMiquel Raynal
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip. Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the driver activates the arbiter by default for all boards (either needed or harmless). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-27arm64: dts: marvell: use reworked NAND controller driver on Armada 7KMiquel Raynal
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip. Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the driver activates the arbiter by default for all boards (either needed or harmless). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-27ARM64: dts: marvell: armada-cp110: Add registers clock for sata nodeGregory CLEMENT
This extra clock is needed to access the registers of the AHCI SATA controller used on the Armada 7K/8K SoCs. The ahci drivers was already designed to support up to 5 clocks so there is only need to update the device tree to use it. It was not noticed until now because of wrong assumption in the clock drivers, but as this IP really needs 2 clocks, we had to declare both of them. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-8080-db: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-8040-mcbin: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-8040-db: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-7040-db: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-3720-espressobin: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: armada-3720-db: use SPDX-License-IdentifierGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCsGregory CLEMENT
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: mcbin: fix board name typoBaruch Siach
A 'C' was missing in the model name, this patch fixes it. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: mcbin: enable uart headersBaruch Siach
Add description of the J25 and J27 UART headers of the Macchiatobin. They use uart peripherals that the CP0 (J25) and CP1 (J27) provide. Even though J25 and J27 are labeled as UART header, the pins on these headers can be muxed for other purposes. But the UART functionality is useful when the board is mounted in an ATX style enclosure, since the console UART is not accessible through the microUSB at CON9. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: add CP110 uart peripheralsBaruch Siach
The CP110 component has 4 uart peripherals. All of them use the same clock gate for slow peripherals that is shared with the i2c and spi peripherals. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodesGregory CLEMENT
This extra clock is needed to access the registers of the I2C controller used on the Armada 7K/8K SoCs. This follows the changes already made in the binding documentation (as well as in the driver) in: commit 1534156e999735fe0befad958e1447600c0c20e7 ("i2c: mv64xxx: Fix clock resource by adding an optional bus clock") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodesGregory CLEMENT
This extra clock is needed to access the registers of the SPI controller used on Armada 7K/8K SoCs. This follows the changes already made in the binding documentation (as well as in the driver) in: 'commit 92ae112e477ac412decc3fdd5c1eeb6c90c266b4 ("spi: orion: Fix clock resource by adding an optional bus clock")'. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-01-12arm64: dts: marvell: armada-80x0: Fix pinctrl compatible stringGregory CLEMENT
When replacing the cpm by cp0 and cps by cp1 [1] not only the label and the alias were replaced but also the compatible string which was wrong. Due to this the pinctrl driver was no more probed. This patch fix it by reverting this change for the pinctrl compatible string on Armada 8K. [1]: "arm64: dts: marvell: replace cpm by cp0, cps by cp1" Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2018-01-05arm64: dts: marvell: add Ethernet aliasesYan Markman
This patch adds Ethernet aliases in the Marvell Armada 7040 DB, 8040 DB and 8040 mcbin device trees so that the bootloader setup the MAC addresses correctly. Signed-off-by: Yan Markman <ymarkman@marvell.com> [Antoine: commit message, small fixes] Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2018-01-05arm64: dts: marvell: replace cpm by cp0, cps by cp1Thomas Petazzoni
In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2018-01-05arm64: dts: marvell: de-duplicate CP110 descriptionThomas Petazzoni
One concept of Marvell Armada 7K/8K SoCs is that they are made of HW blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated several times within a given SoC. The Armada 7K SoC has a single CP110 (so no duplication), while the Armada 8K SoC has two CP110. In the future, SoCs with more than 2 CP110s will be introduced. In current kernel versions, the master CP110 is described in armada-cp110-master.dtsi and the slave CP110 is described in armada-cp110-slave.dtsi. Those files are basically exactly the same, since they describe the same hardware. They only have a few differences: - Base address of the registers is different for the "config-space" - Base address of the PCIe registers, MEM, CONF and IO areas were different - Labels (and phandles pointing to them) of the nodes were different ("cpm" prefix in the master CP, "cps" prefix in the slave CP) This duplication issue has been discussed at the DT workshop [1] in Prague last October, and we presented on this topic [2]. The solution of using the C pre-processor to avoid this duplication has been validated by the people present in this DT workshop, and this patch simply implements what has been presented. We handle differences between the master CP and slave CP description using the C pre-processor, by defining a set of macros with different values armada-cp110.dtsi is included to instantiate one of the master or slave CP110. There are a few aspects that deserve additional explanations: - PCIe needs to be handled separately because it is not part of the config-space {...} node, since it has registers outside of the range covered by config-space {...}. - We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because they are used for the unit address part of some DT nodes. But since they are also used for the "reg" property of the same nodes, we have an ADDRESSIFY() macro that prepends 0x to those values. We compared the resulting .dtb for armada-8040-db.dtb before and after this patch is applied, and the result is exactly the same, except for a few differences: - the SDHCI controller that was only described in the master CP110 is now also described in the slave CP110. Even though the SDHCI controller from the slave CP110 is indeed not usable (as it isn't wired to the outside world) it is technically part of the silicon, and therefore it is reasonable to also describe it to be part of the slave CP110. In addition, if we wanted to get this correct for the SDHCI controller, we should also do it for the NAND controller, for which the situation is even more complicated: in a single CP110 configuration (Armada 7K), the usable NAND controller is in the master CP110, while in a dual CP110 configuration (Armada 8K), the usable NAND controller is in the slave CP110. Since that would add a lot of additional complexity for no good reason, and since the IP blocks are in fact really present in both CPs, we simply describe them in both CPs at the DT level. - the cp110-master and cp110-slave nodes are now named cpm and cps. We could have kept cp110-master and cp110-slave, but that would have required adding another CP110_xyz define, which didn't seem very useful. Note that this commit also gets rid of the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, as future SoCs will have more than 2 CPs. Instead, we instantiate the CPs directly from the SoC-specific .dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi. [1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad [2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf [gregory.clement@free-electrons.com: add back the "ARM64: dts: marvell: Fix clock resources for various node" commit] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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