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2022-02-25arm64: tegra: Drop arm,armv8-pmuv3 compatible stringThierry Reding
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add GPCDMA node for tegra186 and tegra194Akhil R
Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Adjust length of CCPLEX cluster MMIO regionThierry Reding
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra186 compatible string listThierry Reding
The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename thermal zones nodesThierry Reding
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add native timer support on Tegra186Thierry Reding
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194Jon Hunter
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fixup SYSRAM referencesThierry Reding
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Add few AHUB devices for Tegra210 and laterSameer Pujar
Add DT nodes for following AHUB devices: * SFC (Sampling Frequency Converter) * MVC (Master Volume Control) * AMX (Audio Multiplexer) * ADX (Audio Demultiplexer) * Mixer Above devices are added for Tegra210, Tegra186 and Tegra194 generations of Tegra SoC. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-06arm64: tegra: Add NVDEC to Tegra186/194 device treesMikko Perttunen
Add a device tree node for NVDEC on Tegra186, and device tree nodes for NVDEC and NVDEC1 on Tegra194. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add missing interconnects property for USB on Tegra186Thierry Reding
The device tree node for the XUDC (USB device mode controller) is missing the interconnects property that describes the path to memory for the controller. Add the property so that the things like the DMA mask can be set by the operating system. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add PWM nodes on Tegra186Thierry Reding
These PWMs can be used for fan or LED backlight control. Add the device tree nodes for all existing controllers found on Tegra186 SoCs. None of these are enabled by default, which is left for the board DTS files to do when necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11arm64: tegra: Hook up memory controller to SMMU on Tegra186Thierry Reding
On Tegra186 and later, the memory controller needs to be programmed in coordination with any of the ARM SMMU instances to configure the stream ID used for each memory client. To support this, add a phandle reference to the memory controller to the SMMU device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11arm64: tegra: Use correct compatible string for Tegra186 SMMUThierry Reding
The SMMU found on Tegra186 requires interoperation with the memory controller in order to program stream ID overrides. The generic ARM SMMU 500 compatible is therefore inaccurate. Replace it with a more correct, SoC-specific compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-23arm64: tegra: Add unit-address for ACONNECT on Tegra186Thierry Reding
The ACONNECT device tree node has a unit-address on all other SoC generations and there's really no reason not to have it on Tegra186. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-29arm64: tegra: Audio graph sound card for Jetson TX2Sameer Pujar
Enable support for audio-graph based sound card on Jetson TX2. Based on the board design following I/O modules are enabled. * All I2S instances (I2S1 ... I2S6) * All DSPK instances (DSPK1, DSPK2) * DMIC1, DMIC2 and DMIC3 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26arm64: tegra: Enable AHCI on Jetson TX2Sowjanya Komatineni
This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26arm64: tegra: Add XUSB pad controller interruptJC Kuo
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194 XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix GIC400 missing GICH/GICV register regionsMarc Zyngier
GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing CPU PMUs on Tegra186Marc Zyngier
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-10-24Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
2020-09-02arm64: tegra: Add DT binding for AHUB componentsSameer Pujar
This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodesSowjanya Komatineni
commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host capability register and uses it by default. So, this clock should be kept enabled by the SDMMC driver. Fixes: 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-6-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-07-15arm64: tegra: Use standard names for SRAM nodesThierry Reding
SRAM nodes should be named sram@<unit-address> to match the bindings. While at it, also remove the unneeded, custom compatible string for SRAM partition nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark display hub as simple busThierry Reding
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix {clock,reset}-names orderingThierry Reding
It's very difficult to describe string lists that can be in arbitrary order using the json-schema based validation tooling. Since the OS is not going to care either way, take the easy way out and reorder these entries to match the order defined in the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove XUSB pad controller interrupt from XUSB nodeThierry Reding
The XUSB controller doesn't need the XUSB pad controller's interrupt, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark host1x as simple busThierry Reding
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use proper tuple notationThierry Reding
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra186Thierry Reding
The interface used by clients of the memory controller can be configured in a number of different ways. Describe this path using the interconnect bindings to enable the configuration of these parameters. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Use standard notation for interruptsThierry Reding
It is customary to use angle brackets around each tuple in the interrupts property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186Thierry Reding
The standard mmio-sram bindings require the #address- and #size-cells properties to be 1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUDC node for Tegra186Nagarjuna Kristam
Tegra186 has one XUSB device mode controller, which can be operated in HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Make XUSB node consistent with the restThierry Reding
The ordering of properties in the XUSB node is inconsistent with the ordering of the properties in other nodes. Resort them to make the node more consistent. Also get rid of some unnecessary whitespace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Add external memory controller on Tegra186Thierry Reding
Add the external memory controller as a child device of the memory controller on Tegra186. The memory controller really represents the memory subsystem that encompasses both the memory and external memory controllers. The external memory controller uses the BPMP to obtain the list of supported EMC frequencies and set the EMC frequency. Also set up the dma-ranges property to describe that all memory clients can address up to 40 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Add interrupt for memory controller on Tegra186Thierry Reding
The memory controller can be interrupted by certain conditions. Add the interrupt to the device tree node to allow drivers to trap these conditions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix compatible for SOR1Thierry Reding
It turns out that both SORs on Tegra186 are the same, so there's no need to distinguish between them in the compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable SMMU for VIC on Tegra186Thierry Reding
Enable address translation for VIC via the SMMU on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable SMMU for XUSB host on Tegra186Nagarjuna Kristam
Enabling the SMMU for XUSB host allows buffers to be mapped through the ARM SMMU, which helps protecting the system from rogue memory accesses by the XUSB host. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-21arm64: tegra: Add ACONNECT, ADMA and AGIC nodesSameer Pujar
Add device tree nodes for the ACONNECT, ADMA and AGIC devices on Tegra186 and Tegra194. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Sort device tree nodes alphabeticallyThierry Reding
Device tree nodes without unit-address are to be sorted alphabetically. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-14arm64: tegra: Mark architected timer as always onThierry Reding
The architected timer on Tegra186 and Tegra194 is in an always on power partition and its reference clock will always run, so mark the timer as always on. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-05arm64: tegra: Add pin control states for I2C on Tegra186Thierry Reding
Two of the Tegra I2C controllers share pads with the DPAUX controllers. In order for the I2C controllers to use these pads, they have to be set into I2C mode. Use the I2C and off pin control states defined in the DT nodes for DPAUX as "default" and "idle" states, respectively. This ensures that the I2C controller driver can properly configure the pins when it needs to perform I2C transactions. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-05arm64: tegra: Add CPU cache topology for Tegra186Joseph Lo
Tegra186 has two CPU clusters with its own cache hierarchy. This patch adds them with the cache information of each of the CPUs. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-08arm64: tegra: Enable SMMU translation for PCI on Tegra186Thierry Reding
Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") intentionally breaks all devices using the SMMU in bypass mode. This breaks, among other things, PCI support on Tegra186. Fix this by populating the iommus property and friends for the PCIe controller. Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-08arm64: tegra: Fix insecure SMMU users for Tegra186Jonathan Hunter
Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") intentionally breaks all devices using the SMMU in bypass mode. This is breaking various devices on Tegra186 which include the ethernet, BPMP and HDA device. Fix this by populating the iommus property for these devices with their stream ID. Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: Add XUSB and pad controller on Tegra186Thierry Reding
Adds the XUSB pad and XUSB controllers on Tegra186. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Enable command queue for Tegra186 SDMMC4Sowjanya Komatineni
The workaround for a hardware bug preventing this from working has been merged now, so command queue support can be enabled again for Tegra186. Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit (git 2.34.1) at 2025-03-22 10:51:07 +0000