summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/qcom/sm8250.dtsi
AgeCommit message (Collapse)Author
2024-04-12arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocsLuca Weiss
The code in qcom_q6v5_init() requests the "wdog" IRQ as IRQF_TRIGGER_RISING. If dt defines the interrupt type as LEVEL_HIGH then the driver will have issues getting the IRQ again after probe deferral with an error like: irq: type mismatch, failed to map hwirq-14 for interrupt-controller@b220000! Fix that by updating the devicetrees to use IRQ_TYPE_EDGE_RISING for these interrupts, as is already used in most dt's. Also the driver was already using the interrupts with that type. Fixes: 3658e411efcb ("arm64: dts: qcom: sc7280: Add ADSP node") Fixes: df62402e5ff9 ("arm64: dts: qcom: sc7280: Add CDSP node") Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Fixes: 8eb5287e8a42 ("arm64: dts: qcom: sm6350: Add CDSP nodes") Fixes: efc33c969f23 ("arm64: dts: qcom: sm6350: Add ADSP nodes") Fixes: fe6fd26aeddf ("arm64: dts: qcom: sm6375: Add ADSP&CDSP") Fixes: 23a8903785b9 ("arm64: dts: qcom: sm8250: Add remoteprocs") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240219-remoteproc-irqs-v1-1-c5aeb02334bd@fairphone.com [bjorn: Added fixes references] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-18arm64: dts: qcom: replace underscores in node namesKrzysztof Kozlowski
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240213145124.342514-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8250: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8250 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-12-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: split PCIe interrupt-names entries per linesKrzysztof Kozlowski
Other PCIe nodes in SM8250 and SM8350 have one interrupt name per line, so adjust PCIe0 to match the style. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8250: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-2-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8250: Hook up GPU cooling deviceKonrad Dybcio
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-8-fda30c57e353@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targetsKrishna Kurapati
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Also modify order of interrupts in accordance to bindings update. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Fix coresight warnings in in-ports and out-portsMao Jinlong
When a node is only one in port or one out port, address-cells and size-cells are not required in in-ports and out-ports. And the number and reg of the port need to be removed. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Link: https://lore.kernel.org/r/20231210072633.4243-5-quic_jinlmao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Use "pcie" as the node name instead of "pci"Manivannan Sadhasivam
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8250: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sm8250: Add wakeup-source to usb_1 and usb_2Bryan O'Donoghue
To test out a different GDSC change I wanted to have a USB keypress resume a system in suspend. Adding wakeup-source to usb_1 and usb_2 "just works" for me on rb5. Consistent with qcm2290 and sa8775p add wakeup-source to the dtsi for the SoC. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231109004311.2449566-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sm8250: correct Soundwire node nameKrzysztof Kozlowski
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sm8250-xiaomi-elish-boe.dtb: soundwire-controller@3250000: $nodename:0: 'soundwire-controller@3250000' does not match '^soundwire(@.*)?$' Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231107102111.16465-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sm8250: Add TCSR halt register spaceMukesh Ojha
Enable download mode for sm8250 which can help collect ramdump for this SoC. Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1698253601-11957-2-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-02arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggeredDouglas Anderson
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 46a4359f9156 ("arm64: dts: qcom: sm8250: Add watchdog bark interrupt") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.5.I2910e7c10493d896841e9785c1817df9b9a58701@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-02arm64: dts: qcom: sm8250: Add OPP table support to UFSHCManivannan Sadhasivam
UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231012172129.65172-6-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-11-14arm64: dts: qcom: sm8250: switch USB QMP PHY to new style of bindingsDmitry Baryshkov
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230824211952.1397699-14-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sm8250: switch PCIe QMP PHY to new style of bindingsDmitry Baryshkov
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-17-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sm8250: Add DisplayPort device nodeDmitry Baryshkov
Declare the displayport controller present on the Qualcomm SM8250 SoC. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230817145940.9887-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: qrb5165-rb5: Switch on TCPM orientation-switch for ↵Bryan O'Donoghue
usb_1_qmpphy Switch on USB orientation-switching for usb_1_qmp via TCPM. Detecting the orientation switch is required to get the PHY to reset and bring-up the PHY with the CC lines set to the appropriate lane. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230816115151.501736-8-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: qrb5165-rb5: Switch on TCPM usb-role-switching for usb_1Bryan O'Donoghue
Switch on usb-role-switching for usb_1 via TCPM. We need to declare usb-role-switch in &usb_1 and associate with the remote-endpoint in TCPM which provides the necessary signal. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230816115151.501736-7-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sm8250: Define ports for qmpphy orientation-switchingBryan O'Donoghue
ports for orientation switching input and output. The individual board dts files will instantiate port@0, port@1 and/or port@2 depending on the supported feature-set. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230816115151.501736-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-15arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPsKonrad Dybcio
Describe the interconnect paths related to QUPs and add the power-domains powering them. This is required for icc sync_state, as otherwise QUP access is gated. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230703-topic-8250_qup_icc-v2-4-9ba0a9460be2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-14arm64: dts: qcom: sm8250: switch USB+DP QMP PHY to new style of bindingsDmitry Baryshkov
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-11-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-30Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM devicetree updates from Arnd Bergmann: "These are the devicetree updates for Arm and RISC-V based SoCs, mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and Starfive. Only a few new SoC got added: - TI AM62P5, a variant of the existing Sitara AM62x family - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55 SoC. - Qualcomm ipq5018 is used in wireless access points - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone platform. In total, 29 machines get added, which is low because of the summer break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST, Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of these are development and reference boards. Despite not adding a lot of new machines, there are over 700 patches in total, most of which are cleanups and minor fixes" * tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits) arm64: dts: use capital "OR" for multiple licenses in SPDX ARM: dts: use capital "OR" for multiple licenses in SPDX arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved ARM: dts: qcom: apq8064: add support to gsbi4 uart riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs ARM: dts: stm32: support display on stm32f746-disco board ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco ARM: dts: stm32: add pin map for LTDC on stm32f7 ARM: dts: stm32: add ltdc support on stm32f746 MCU arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Add PDC riscv: dts: starfive: fix jh7110 qspi sort order ...
2023-07-21arm64: dts: qcom: sm8250: Add interconnect paths to UFSHCManivannan Sadhasivam
UFS host controller requires interconnect path configuration for proper working. So let's specify them for SM8250 SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230720054100.9940-14-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-21arm64: dts: qcom: sm8250: Update the RPMHPD bindings entryRohit Agarwal
Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8250 SoC. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1689840545-5094-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-13arm64: dts: qcom: sm8250: Add BWMONsKonrad Dybcio
Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm8250. LPDDR4X levels are skipped, as LPDDR5 seems more popular with SM8250 and voting for inexistent levels doesn't uptick the bus frequency, which results in no increased bandwidth, which results in bwmon deciding we shouldn't go higher.. you see the point! Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230711-topic-sm638250_bwmon-v1-3-bd4bb96b0673@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8250: Mark SMMUs as DMA coherentKonrad Dybcio
The SMMUs on SM8250 are cache-coherent. Mark them as such. Fixes: a89441fcd09d ("arm64: dts: qcom: sm8250: add apps_smmu node") Fixes: 04a3605b184e ("arm64: dts: qcom: add sm8250 GPU nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230704-topic-8250_pcie_dmac-v1-2-799603a980b0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8250: Mark PCIe hosts as DMA coherentKonrad Dybcio
The PCIe hosts on SM8250 are cache-coherent. Mark them as such. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230704-topic-8250_pcie_dmac-v1-1-799603a980b0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8250: correct dynamic power coefficientsVincent Guittot
sm8250 faces the same problem with its Energy Model as sdm845. The energy cost of LITTLE cores is reported to be higher than medium or big cores EM computes the energy with formula: energy = OPP's cost / maximum cpu capacity * utilization On v6.4-rc6 we have: max capacity of CPU0 = 284 capacity of CPU0's OPP(1612800 Hz) = 253 cost of CPU0's OPP(1612800 Hz) = 191704 max capacity of CPU4 = 871 capacity of CPU4's OPP(710400 Hz) = 255 cost of CPU4's OPP(710400 Hz) = 343217 Both OPPs have almost the same compute capacity but the estimated energy per unit of utilization will be estimated to: energy CPU0 = 191704 / 284 * 1 = 675 energy CPU4 = 343217 / 871 * 1 = 394 EM estimates that little CPU0 will consume 71% more than medium CPU4 for the same compute capacity. According to [1], little consumes 25% less than medium core for Coremark benchmark at those OPPs for the same duration. Set the dynamic-power-coefficient of CPU0-3 to 105 to fix the energy model for little CPUs. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sm8250/k30s Fixes: 6aabed5526ee ("arm64: dts: qcom: sm8250: Add CPU capacities and energy model") Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Link: https://lore.kernel.org/r/20230615154852.130076-1-vincent.guittot@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8250: Fix EPSS L3 interconnect cellsKrzysztof Kozlowski
Qualcomm EPSS L3 Interconnect does not take path (third) argument. This was introduced by commit b5a12438325b ("arm64: dts: qcom: sm8250: Use 2 interconnect cells") which probably wanted to use 2 cells only for RPMh interconnects. sm8250-hdk.dtb: interconnect@18590000: #interconnect-cells:0:0: 1 was expected Fixes: b5a12438325b ("arm64: dts: qcom: sm8250: Use 2 interconnect cells") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230617204118.61959-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-06-13arm64: dts: qcom: sm8250: rename labels for DSI nodesDmitry Baryshkov
Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230531011623.3808538-13-dmitry.baryshkov@linaro.org
2023-06-13arm64: dts: qcom: sm8250: Add missing interconnect paths to USB HCsAbel Vesa
The USB HCs nodes are missing the interconnect paths, so add them. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230602062016.1883171-4-abel.vesa@linaro.org
2023-06-13arm64: dts: qcom: sm8250: Use 2 interconnect cellsAbel Vesa
Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230602062016.1883171-3-abel.vesa@linaro.org
2023-05-26arm64: dts: qcom: sm8250: add missing qcom,smmu-500 fallbackKrzysztof Kozlowski
Since commit 6c84bbd103d8 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback: ['qcom,sm8250-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2'] 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416123730.300863-4-krzysztof.kozlowski@linaro.org
2023-05-26arm64: dts: qcom: sm8250: Add Crypto Engine supportBhupesh Sharma
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8250.dtsi'. Co-developed-by and Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Anders Roxell <anders.roxell@linaro.org> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526192210.3146896-10-bhupesh.sharma@linaro.org
2023-04-07arm64: dts: qcom: sm8250: Add GPU speedbin supportKonrad Dybcio
SM8250 has (at least) four GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7) Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org
2023-04-07arm64: dts: qcom: sm8250: remove superfluous "input-enable"Krzysztof Kozlowski
Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407175807.124394-9-krzysztof.kozlowski@linaro.org
2023-04-06arm64: dts: qcom: Remove "iommus" property from PCIe nodesManivannan Sadhasivam
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
2023-04-06arm64: dts: qcom: sm8250: simplify interrupts-extendedKrzysztof Kozlowski
The parent controller for the interrupt is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-4-krzysztof.kozlowski@linaro.org
2023-04-04arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodesManivannan Sadhasivam
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org
2023-04-04arm64: dts: qcom: sm8250: drop incorrect domain idle states propertiesKrzysztof Kozlowski
Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8250-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230324073813.22158-1-krzysztof.kozlowski@linaro.org
2023-03-21arm64: dts: qcom: drop redundant line breaksKrzysztof Kozlowski
Remove trailing, redundant line breaks. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org
2023-03-15arm64: dts: qcom: sm8250: Fix the PCI I/O port rangeManivannan Sadhasivam
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000, 0x64200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-9-manivannan.sadhasivam@linaro.org
2023-03-15arm64: dts: qcom: sm8250: Add tpdm mm/prngMao Jinlong
Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117145708.16739-10-quic_jinlmao@quicinc.com
2023-03-15arm64: dts: qcom: sm8250: drop incorrect Coresight funnel propertiesKrzysztof Kozlowski
There is only one output port, thus out-ports should not have 'address/size-cells' and unit addresses. 'reg-names' are also not allowed by bindings. qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+' qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org
2023-03-15arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banksManivannan Sadhasivam
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org
2023-03-14arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMUKonrad Dybcio
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230216145646.4095336-4-konrad.dybcio@linaro.org
2023-03-14arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUsManivannan Sadhasivam
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230215070400.5901-6-manivannan.sadhasivam@linaro.org
generated by cgit (git 2.34.1) at 2024-06-10 16:10:59 +0000