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2024-06-21arm64: dts: qcom: sm8450: drop second clock name from clock-output-namesDmitry Baryshkov
There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. The driver generates it on its own, in order to remain compatible with the older DT. Drop the clock name. Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-3-730d1811acf4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm8450: Throttle the GPU when overheatingKonrad Dybcio
Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Remove the copypasta-from-downstream userspace governor entries while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-10-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm8450-*: Remove thermal zone polling delaysKonrad Dybcio
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-29-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC blockUnnathi Chalicheemala
Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8450. Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com> Link: https://lore.kernel.org/r/bfc817da4188abdf5b543bedafb9cb0eb82806c2.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-28arm64: dts: qcom: sm8450: Add OPP table support to PCIeKrishna chaitanya chundru
PCIe host controller driver needs to choose the appropriate performance state of RPMh power domain and interconnect bandwidth based on the PCIe data rate. Hence, add the OPP table support to specify RPMh performance states and interconnect peak bandwidth. It should be noted that the different link configurations may share the same aggregate bandwidth, e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same bandwidth and share the same OPP entry. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/20240518-opp_support-v13-4-78c73edf50de@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-28arm64: dts: qcom: sm8450: Add interconnect path to PCIe nodeKrishna chaitanya chundru
Add PCIe-MEM & CPU-PCIe interconnect path to the PCIe nodes. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/20240518-opp_support-v13-1-78c73edf50de@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-11-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gccNeil Armstrong
The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-1-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: move PHY's orientation-switch to SoC dtsiDmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-7-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-3-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-13Merge tag 'soc-dt-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "The updates this time are a bit smaller than most times, mainly because it is not totally dominated by new Qualcomm hardware support. Instead, we larger than average updates for Rockchips, NXP, Allwinner and TI. The only two new SoCs this time are both from NXP and are minor variants of already supported ones. The updates for aspeed, amlogic and mediatek came a little late, so I'm saving those for part 2 in a few days if everything turns out fine. New machines this time contain: - two Broadcom SoC based wireless routers from Asus - Five allwinner based consumer devices for gaming, set-top-box and eboot reader applications - Three older phones based on Qualcomm chips, plus the more recent Sony Xperia 1 V - 14 industrial and embedded boards based on NXP i.MX6, i.MX8, layerscape and s32g3 SoCs - six rockchips boards including another handheld game console and a few single-board computers On top of these, we have the usual cleanups for dtc warnings and updates to add more features to already merged machines" * tag 'soc-dt-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (612 commits) arm64: dts: marvell: espressobin-ultra: fix Ethernet Switch unit address arm64: dts: marvell: turris-mox: drop unneeded flash address/size-cells arm64: dts: marvell: eDPU: drop redundant address/size-cells arm64: dts: qcom: pm6150: correct USB VBUS regulator compatible arm64: dts: rockchip: add rk3588 pcie and php IOMMUs arm64: dts: rockchip: enable onboard spi flash for rock-3a arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5 arm64: dts: rockchip: Enable GPU on Orange Pi 5 arm64: dts: rockchip: enable GPU on khadas-edge2 arm64: dts: rockchip: Add USB3 on Edgeble NCM6A-IO board arm64: dts: rockchip: Support poweroff on Edgeble Neural Compute Module arm64: dts: rockchip: Add Radxa ROCK 3C dt-bindings: arm: rockchip: add Radxa ROCK 3C arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive arm64: dts: Add/fix /memory node unit-addresses arm64: dts: qcom: qcs404: fix bluetooth device address arm64: dts: qcom: sc8280xp-x13s: enable USB MP and fingerprint reader ...
2024-04-21arm64: dts: qcom: sm8450: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-12arm64: dts: qcom: sm8450: Fix the msi-map entriesManivannan Sadhasivam
While adding the GIC ITS MSI support, it was found that the msi-map entries needed to be swapped to receive MSIs from the endpoint. But later it was identified that the swapping was needed due to a bug in the Qualcomm PCIe controller driver. And since the bug is now fixed with commit bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly"), let's fix the msi-map entries also to reflect the actual mapping in the hardware. Cc: stable@vger.kernel.org # 6.3: bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly") Fixes: ff384ab56f16 ("arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240318-pci-bdf-sid-fix-v1-1-acca6c5d9cf1@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain propertyNeil Armstrong
By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 91d70eb70867 ("arm64: dts: qcom: sm8450: add fastrpc nodes") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-1-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node namesKrzysztof Kozlowski
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240212172335.124845-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: describe all PCI MSI interruptsKrzysztof Kozlowski
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-4-0bb067f73adb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: Add missing interconnects to serialKonrad Dybcio
The serial ports did not have their interconnect paths specified when they were first introduced. Fix that. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Fixes: f5837418479a ("arm64: dts: qcom: sm8450: add uart20 node") Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Georgi Djakov <djakov@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240116-topic-8450serial-v1-1-b685e6a5ad78@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: sm8450: Hook up GPU cooling deviceKonrad Dybcio
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-10-fda30c57e353@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targetsKrishna Kurapati
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Also modify order of interrupts in accordance to bindings update. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec macrosKrzysztof Kozlowski
The MCLK clocks of codec macros have fixed 19.2 MHz frequency and assigning clock rates is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231213162856.188566-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodesKrzysztof Kozlowski
Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231213162856.188566-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Use "pcie" as the node name instead of "pci"Manivannan Sadhasivam
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8450: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-10-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8450: Add GPU nodesKonrad Dybcio
Add the required nodes to support the A730 GPU. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-2-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sm8450: fix soundwire controllers node nameNeil Armstrong
Fix the following dt bindings check: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: soundwire-controller@31f0000: $nodename:0: 'soundwire-controller@31f0000' does not match '^soundwire(@.*)?$' from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml# Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8450-upstream-soundwire-bindings-fix-v1-1-41d4844a5a7d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-02arm64: dts: qcom: sm8450: correct TX Soundwire clockKrzysztof Kozlowski
The TX Soundwire controller should take clock from TX macro codec, not VA macro codec clock, otherwise the clock stays disabled. This looks like a copy-paste issue, because the SC8280xp code uses here correctly clock from TX macro. The VA macro clock is already consumed by TX macro codec, thus it won't be disabled by this change. Fixes: 14341e76dbc7 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231129140537.161720-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-15arm64: dts: qcom: sm8450: add TRNG nodeNeil Armstrong
The SM8450 SoC has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20231003-topic-sm8550-rng-v4-5-255e4d0ba08e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20Revert "arm64: dts: qcom: sm8450: Add PRNG"Neil Armstrong
This reverts commit 76a6dd7bfcbb ("arm64: dts: qcom: sm8450: Add PRNG"), since the RNG HW on the SM8450 SoC is in fact a True Random Number Generator, a more appropriate compatible should be instead as reported at [1]. [1] https://lore.kernel.org/all/20230818161720.3644424-1-quic_omprsing@quicinc.com/ Suggested-by: Om Prakash Singh <quic_omprsing@quicinc.com> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230828-topic-sm8550-rng-v3-1-7a0678ca7988@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindingsDmitry Baryshkov
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). As a part of this conversion also change the "refgen" name to more correct "rchng". Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-18-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: Use QCOM_SCM_VMID defines for qcom,vmidLuca Weiss
Since we have those defines available in a header, let's use them everywhere where qcom,vmid property is used. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230818-qcom-vmid-defines-v1-1-45b610c96b13@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-13arm64: dts: qcom: sm8450: Add RPMh statsKonrad Dybcio
SM8450 also exposes RPMh stats, hook them up for low power state monitoring. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230811-topic-8450_stats-v1-1-f26ae3fdf2cf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-13arm64: dts: qcom: sm8450: Add PRNGKonrad Dybcio
Add the Qualcomm Pseudo-Random Number Generator. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230811-topic-8450_prng-v1-3-01becceeb1ee@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-21arm64: dts: qcom: sm8450: Update the RPMHPD bindings entryRohit Agarwal
Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8450 SoC. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1689840545-5094-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-13arm64: dts: qcom: sm8450: provide MDSS cfg interconnectDmitry Baryshkov
Add support for the MDSS cfg-cpu bus vote on the SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230712121145.1994830-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8450: Use standalone ICE node for UFSLuca Weiss
With the ICE driver now merged let's convert the ufs node to use the new style. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20221209-dt-binding-ufs-v5-5-c9a58c0a53f5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sm8450: correct crypto unit addressKrzysztof Kozlowski
Crypto node unit address should match reg. Fixes: b92b0d2f7582 ("arm64: dts: qcom: sm8450: add crypto nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230616174955.1783652-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-06-13arm64: dts: qcom: sm8450: Add missing interconnect paths to USB HCAbel Vesa
The USB HC node is missing the interconnect paths, so add them. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230602062016.1883171-6-abel.vesa@linaro.org
2023-05-26arm64: dts: qcom: sm8450: add crypto nodesNeil Armstrong
Add crypto engine (CE) and CE BAM related nodes and definitions for the SM8450 SoC. Tested-by: Anders Roxell <anders.roxell@linaro.org> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> [Bhupesh: Corrected the compatible list] Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526192210.3146896-12-bhupesh.sharma@linaro.org
2023-05-24arm64: dts: qcom: sm8450: Add missing RPMhPD OPP levelsKonrad Dybcio
We need more granularity for things like the GPU. Add the missing levels. This unfortunately requires some re-indexing, resulting in an ugly diff. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516005306.952821-1-konrad.dybcio@linaro.org
2023-05-24arm64: dts: qcom: sm8450: Add video clock controllerTaniya Das
Add device node for video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524140656.7076-4-quic_tdas@quicinc.com
2023-05-23arm64: dts: qcom: sm8450: add ports subnodes in usb1 qmpphy nodeNeil Armstrong
Add the USB3+DP Combo QMP PHY port subnodes in the SM8450 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-2-6c43d293995f@linaro.org
2023-05-17arm64: dts: qcom: add missing cache propertiesKrzysztof Kozlowski
Add required cache-level and cache-unified properties to fix warnings like: qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
2023-05-17arm64: dts: qcom: fix indentationKrzysztof Kozlowski
Correct indentation to use only tabs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-1-krzysztof.kozlowski@linaro.org
2023-04-07arm64: dts: qcom: sm8450: remove superfluous "input-enable"Krzysztof Kozlowski
Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407175807.124394-10-krzysztof.kozlowski@linaro.org
2023-04-06arm64: dts: qcom: Remove "iommus" property from PCIe nodesManivannan Sadhasivam
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
2023-04-06arm64: dts: qcom: sm8450: simplify interrupts-extendedKrzysztof Kozlowski
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-5-krzysztof.kozlowski@linaro.org
2023-04-06arm64: dts: qcom: sm8450: label the Soundwire nodesKrzysztof Kozlowski
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org
2023-04-04arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodesNeil Armstrong
Fixes the following DT bindings check error: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org
generated by cgit (git 2.34.1) at 2025-06-02 14:37:13 +0000